From: Luke Kenneth Casson Leighton Date: Tue, 4 Dec 2018 07:44:04 +0000 (+0000) Subject: record conversation snippet X-Git-Tag: convert-csv-opcode-to-binary~4816 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f2b67f23d2666e345787aff92e5e2acf2ecbf03;p=libreriscv.git record conversation snippet --- diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 424986b3d..f2c363d42 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -147,6 +147,24 @@ length equal to the number of registers, 2 is because of 2-issue). ROBnum, value: instr-dest-reg. if you have a bitfleid that says "this destreg has no ROB tag", it's dead-easy to check that bitfield, first. +---- + +Avoiding Memory Hazards + +* WAR and WAR hazards through memory are eliminated with speculation +because actual updating of memory occurs in order, when a store is at +the head of the ROB, and hence, no earlier loads or stores can still +be pending +* RAW hazards are maintained by two restrictions: + 1. not allowing a load to initiate the second step of its execution if + any active ROB entry occupied by a store has a destination + field that matches the value of the A field of the load and + 2. maintaining the program order for the computation of an effective + address of a load with respect to all earlier stores +* These restrictions ensure that any load that access a memory location + written to by an earlier store cannot perform the memory access until + the store has written the data. + # References *