From: Luke Kenneth Casson Leighton Date: Thu, 18 Oct 2018 22:14:36 +0000 (+0100) Subject: redirect sreg_t casts through function X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f2ea875584c460a075f311301626017226394bd;p=riscv-isa-sim.git redirect sreg_t casts through function --- diff --git a/riscv/insns/auipc.h b/riscv/insns/auipc.h index 1a2b169..0169786 100644 --- a/riscv/insns/auipc.h +++ b/riscv/insns/auipc.h @@ -1 +1 @@ -WRITE_RD(sext_xlen(insn.u_imm() + pc)); +WRITE_RD(sext_xlen(rv_add(insn.u_imm(), pc))); diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h index 8cd7e31..dd8969f 100644 --- a/riscv/insns/bge.h +++ b/riscv/insns/bge.h @@ -1,2 +1,2 @@ -if(rv_ge(sreg_t(RS1), sreg_t(RS2))) +if(rv_ge(sv_reg_to_sreg(RS1), sv_reg_to_sreg(RS2))) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h index 85b0be6..9e8d1c3 100644 --- a/riscv/insns/blt.h +++ b/riscv/insns/blt.h @@ -1,2 +1,2 @@ -if(rv_lt(sreg_t(RS1), sreg_t(RS2))) +if(rv_lt(sv_reg_to_sreg(RS1), sv_reg_to_sreg(RS2))) set_pc(BRANCH_TARGET);