From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 17:22:14 +0000 (-0700)
Subject: Do not call "setundef -zero" in abc9
X-Git-Tag: working-ls180~1237^2~83
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f34779d64bbaee7210b567d4ad9ced456f0e159;p=yosys.git

Do not call "setundef -zero" in abc9
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2f670dba2..fc9da1173 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -380,9 +380,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		RTLIL::Selection& sel = design->selection_stack.back();
 		sel.select(module);
 
-		// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
-		Pass::call(design, "setundef -zero");
-
 		Pass::call(design, "aigmap");
 
 		handle_loops(design);
@@ -406,7 +403,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			reader.parse_xaiger();
 		}
 		ifs.close();
-		Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v"));
+		Pass::call(design, stringf("write_verilog -noexpr -norename"));
 		design->remove(design->module("$__abc9__"));
 #endif
 
@@ -479,7 +476,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		ifs.close();
 
 #if 0
-		Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v"));
+		Pass::call(design, stringf("write_verilog -noexpr -norename"));
 #endif
 
 		log_header(design, "Re-integrating ABC9 results.\n");