From: lkcl <lkcl@web>
Date: Mon, 10 Apr 2023 21:31:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f356aaac576351ee9d91a55ce5aadd4bc89cc9a;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index cb260ce21..aeddefd60 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -33,7 +33,8 @@ the following Modes apply to Arithmetic and Logical SVP64 operations:
   for both INT and FP.
 * **reduce mode**. If used correctly, a mapreduce (or a prefix sum)
   is performed. See [[svp64/appendix]].
-  Note that there are comprehensive caveats when using this mode.
+  Note that there are comprehensive caveats when using this mode,
+  and it should not be confused with the Parallel Reduction [[sv/remap]].
 * **pred-result** will test the result (CR testing selects a bit of CR
   and inverts it, just like branch conditional testing) and if the
   test fails it is as if the *destination* predicate bit was zero even