From: Alan Modra <amodra@gmail.com>
Date: Thu, 13 May 1999 06:00:13 +0000 (+0000)
Subject: ÿ
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f4438abfd180700f3e27c2caf44bd38ee5ad7c9;p=binutils-gdb.git

ÿ
i386 PIII SIMD support, remove ReverseRegRegmem kludge
tidy a few things in i386 intel mode disassembly
---

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index dcbfc7e2f87..e4a36911eec 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -740,7 +740,7 @@ pi (line, x)
       pt (x->types[i]);
       fprintf (stdout, "\n");
       if (x->types[i]
-	  & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX))
+	  & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
 	fprintf (stdout, "%s\n", x->regs[i]->reg_name);
       if (x->types[i] & Imm)
 	pe (x->imms[i]);
@@ -835,6 +835,7 @@ type_names[] =
   { Acc, "Acc" },
   { JumpAbsolute, "Jump Absolute" },
   { RegMMX, "rMMX" },
+  { RegXMM, "rXMM" },
   { EsSeg, "es" },
   { 0, "" }
 };
@@ -1552,8 +1553,10 @@ md_assemble (line)
 		    continue;
 		  }
 		/* Any other register is bad */
-		if (i.types[op] & (Reg | RegMMX | Control | Debug | Test
-				   | FloatReg | FloatAcc | SReg2 | SReg3))
+		if (i.types[op] & (Reg | RegMMX | RegXMM
+				   | SReg2 | SReg3
+				   | Control | Debug | Test
+				   | FloatReg | FloatAcc))
 		  {
 		    as_bad (_("`%%%s' not allowed with `%s%c'"),
 			    i.regs[op]->reg_name,
@@ -1740,12 +1743,12 @@ md_assemble (line)
           }
       }
 
-    if (i.tm.base_opcode == AMD_3DNOW_OPCODE)
+    if (i.tm.opcode_modifier & ImmExt)
       {
-	/* These AMD specific instructions have an opcode suffix which
-	   is coded in the same place as an 8-bit immediate field
-	   would be.  Here we fake an 8-bit immediate operand from the
-	   opcode suffix stored in tm.extension_opcode.  */
+	/* These AMD 3DNow! and Intel Katmai New Instructions have an
+	   opcode suffix which is coded in the same place as an 8-bit
+	   immediate field would be.  Here we fake an 8-bit immediate
+	   operand from the opcode suffix stored in tm.extension_opcode.  */
 
 	expressionS *exp;
 
@@ -1822,37 +1825,21 @@ md_assemble (line)
 	      {
 		unsigned int source, dest;
 		source = ((i.types[0]
-			   & (Reg
-			      | SReg2
-			      | SReg3
-			      | Control
-			      | Debug
-			      | Test
-			      | RegMMX))
+			   & (Reg | RegMMX | RegXMM
+			      | SReg2 | SReg3
+			      | Control | Debug | Test))
 			  ? 0 : 1);
 		dest = source + 1;
 
-		/* Certain instructions expect the destination to be
-		   in the i.rm.reg field.  This is by far the
-		   exceptional case.  For these instructions, if the
-		   source operand is a register, we must reverse the
-		   i.rm.reg and i.rm.regmem fields.  We accomplish
-		   this by pretending that the two register operands
-		   were given in the reverse order.  */
-		if (i.tm.opcode_modifier & ReverseRegRegmem)
-		  {
-		    const reg_entry *tmp = i.regs[source];
-		    i.regs[source] = i.regs[dest];
-		    i.regs[dest] = tmp;
-		  }
-
 		i.rm.mode = 3;
-		/* We must be careful to make sure that all
-		   segment/control/test/debug/MMX registers go into
-		   the i.rm.reg field (despite whether they are
-		   source or destination operands). */
-		if (i.regs[dest]->reg_type
-		    & (SReg2 | SReg3 | Control | Debug | Test | RegMMX))
+		/* One of the register operands will be encoded in the
+		   i.tm.reg field, the other in the combined i.tm.mode
+		   and i.tm.regmem fields.  If no form of this
+		   instruction supports a memory destination operand,
+		   then we assume the source operand may sometimes be
+		   a memory operand and so we need to store the
+		   destination in the i.rm.reg field.  */
+		if ((i.tm.operand_types[dest] & AnyMem) == 0)
 		  {
 		    i.rm.reg = i.regs[dest]->reg_num;
 		    i.rm.regmem = i.regs[source]->reg_num;
@@ -1999,12 +1986,14 @@ md_assemble (line)
 		  {
 		    unsigned int op =
 		      ((i.types[0]
-			& (Reg | SReg2 | SReg3 | Control | Debug
-			   | Test | RegMMX))
+			& (Reg | RegMMX | RegXMM
+			   | SReg2 | SReg3
+			   | Control | Debug | Test))
 		       ? 0
 		       : ((i.types[1]
-			   & (Reg | SReg2 | SReg3 | Control | Debug
-			      | Test | RegMMX))
+			   & (Reg | RegMMX | RegXMM
+			      | SReg2 | SReg3
+			      | Control | Debug | Test))
 			  ? 1
 			  : 2));
 		    /* If there is an extension opcode to put here, the