From: lkcl <lkcl@web>
Date: Wed, 18 May 2022 12:53:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f4e9f77568099c398cf6a89b2e76a0674620900;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 4272e05f4..7514e0901 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -8,9 +8,11 @@
 
 SV is designed as a Vector ISA for Hybrid 3D CPU GPU VPU workloads.
 As such it brings features normally only found in Cray Supercomputers
-and GPUs, but keeps strictly to a *Simple* principle of leveraging
+(Cray-1, NEC SX-Aurora)
+and in GPUs, but keeps strictly to a *Simple* principle of leveraging
 a *Scalar* ISA, exclisively using "Prefixing". **Not one single actual
 explicit Vector opcode exists in SV, at all**.
+
 Fundamental design principles:
 
 * Simplicity of introduction and implementation on the existing OpenPOWER ISA