From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Oct 2018 03:38:37 +0000 (+0100)
Subject: add f64 redirection to sv_proc_t
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f5a70b8f263bebfb89ee6f1a77f8ad5e01d544b;p=riscv-isa-sim.git

add f64 redirection to sv_proc_t
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5eb4f07..4db6ca6 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -154,7 +154,7 @@ reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec)
     {
         ndata = data >> (shift*bitwidth); // gets element within the reg-block
         ndata &= ((1UL<<bitwidth)-1UL); // masks off the right bits
-        fprintf(stderr, "readreg %lx bitwidth %d offs %d shift %d %lx->%lx\n",
+        fprintf(stderr, "readreg %ld bitwidth %d offs %d shift %d %lx->%lx\n",
                         spec.reg, bitwidth, offs, shift, data, ndata);
     }
     return ndata;
@@ -698,3 +698,70 @@ sv_reg_t (sv_proc_t::mulhu)(sv_reg_t const& a, sv_reg_t const& b)
 }
 
 
+float64_t (sv_proc_t::f64_add)( float64_t a, float64_t b )
+{
+    return ::f64_add(a, b);
+}
+
+
+float64_t (sv_proc_t::f64_sub)( float64_t a, float64_t b )
+{
+    return ::f64_sub(a, b);
+}
+
+float64_t (sv_proc_t::f64_mul)( float64_t a, float64_t b )
+{
+    return ::f64_mul(a, b);
+}
+
+float64_t (sv_proc_t::f64_mulAdd)( float64_t a, float64_t b , float64_t c)
+{
+    return ::f64_mulAdd(a, b, c);
+}
+
+float64_t (sv_proc_t::f64_div)( float64_t a, float64_t b )
+{
+    return ::f64_div(a, b);
+}
+
+float64_t (sv_proc_t::f64_rem)( float64_t a, float64_t b )
+{
+    return ::f64_rem(a, b);
+}
+
+float64_t (sv_proc_t::f64_sqrt)( float64_t a )
+{
+    return ::f64_sqrt(a);
+}
+
+bool (sv_proc_t::f64_eq)( float64_t a, float64_t b )
+{
+    return ::f64_eq(a, b);
+}
+
+bool (sv_proc_t::f64_le)( float64_t a, float64_t b )
+{
+    return ::f64_le(a, b);
+}
+
+bool (sv_proc_t::f64_lt)( float64_t a, float64_t b )
+{
+    return ::f64_lt(a, b);
+}
+
+bool (sv_proc_t::f64_eq_signaling)( float64_t a, float64_t b )
+{
+    return ::f64_eq_signaling(a, b);
+}
+
+bool (sv_proc_t::f64_le_quiet)( float64_t a, float64_t b )
+{
+    return ::f64_le_quiet(a, b);
+}
+
+bool (sv_proc_t::f64_lt_quiet)( float64_t a, float64_t b )
+{
+    return ::f64_lt_quiet(a, b);
+}
+
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 11537f3..6df0e00 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -212,6 +212,21 @@ public:
     sv_reg_t (mulhu)(sv_reg_t const& a, sv_reg_t const& b);
     sv_sreg_t (mulh)(sv_sreg_t const& a, sv_sreg_t const& b);
 
+    float64_t f64_add( float64_t, float64_t );
+    float64_t f64_sub( float64_t, float64_t );
+    float64_t f64_mul( float64_t, float64_t );
+    float64_t f64_mulAdd( float64_t, float64_t, float64_t );
+    float64_t f64_div( float64_t, float64_t );
+    float64_t f64_rem( float64_t, float64_t );
+    float64_t f64_sqrt( float64_t );
+    bool f64_eq( float64_t, float64_t );
+    bool f64_le( float64_t, float64_t );
+    bool f64_lt( float64_t, float64_t );
+    bool f64_eq_signaling( float64_t, float64_t );
+    bool f64_le_quiet( float64_t, float64_t );
+    bool f64_lt_quiet( float64_t, float64_t );
+
+
 
 #include "sv_insn_decl.h"
 };