From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 21:51:10 +0000 (-0700)
Subject: Fix for when B_SIGNED = 1
X-Git-Tag: working-ls180~1208^2~362
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f5dab0d09f881d78fca73c54c20118c52b2e563;p=yosys.git

Fix for when B_SIGNED = 1
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index ff33cf8ff..758d2ade3 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -28,12 +28,19 @@ module \$shiftx (A, B, Y);
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
 
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
   generate
     genvar i;
     if (B_WIDTH < 3) begin
-      reg _TECHMAP_FAIL_;
+      wire _TECHMAP_FAIL_;
       assign _TECHMAP_FAIL_ = 1;
     end
+    // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+    else if (B_SIGNED && _TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) begin
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+    end
     else if (B_WIDTH == 3) begin
       localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1));
       localparam a_widthN = A_WIDTH - a_width0;