From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Apr 2019 07:59:11 +0000 (+0200)
Subject: Merge pull request #910 from ucb-bar/memupdates
X-Git-Tag: yosys-0.9~209
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f6554d698b8857c47e7cc9b452517dd7cbbee6b;p=yosys.git

Merge pull request #910 from ucb-bar/memupdates

Refine memory support to deal with general Verilog memory definitions.
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3f6554d698b8857c47e7cc9b452517dd7cbbee6b