From: Luke Kenneth Casson Leighton Date: Wed, 19 May 2021 13:19:11 +0000 (+0100) Subject: resolve merge conflicts, effectively reverting "verbose" setting X-Git-Tag: xlen-bcd~590 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f706e35bcb2b20d28d8c99bdeecdf51ebd3bae1;p=openpower-isa.git resolve merge conflicts, effectively reverting "verbose" setting because it's critically essential at this stage ../openpower/isatables/ update SVP64 CSV tables --- diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv index 43ef6327..c25ff8f0 100644 --- a/openpower/isatables/LDSTRM-2P-1S2D.csv +++ b/openpower/isatables/LDSTRM-2P-1S2D.csv @@ -3,6 +3,6 @@ lwzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lbzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhau,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA -lfsu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA -lfdu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA +lfsu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,RA +lfdu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,RA ldu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv index 248c4835..ba4f71e2 100644 --- a/openpower/isatables/LDSTRM-2P-2S1D.csv +++ b/openpower/isatables/LDSTRM-2P-2S1D.csv @@ -23,8 +23,8 @@ lfiwzx,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 stwu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA stbu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA sthu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA -stfsu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA -stfdu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA +stfsu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,RA +stfdu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,RA stdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA ldux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA @@ -32,11 +32,11 @@ lbzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA -lfsux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA -lfdux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA +lfsux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA +lfdux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA stdux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA stwux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA stbux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA sthux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stfsux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA -stfdux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA +stfsux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA,RB,FRS,0,0,0,RA +stfdux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA,RB,FRS,0,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv index 41f14bf1..83e2663e 100644 --- a/openpower/isatables/LDSTRM-2P-3S.csv +++ b/openpower/isatables/LDSTRM-2P-3S.csv @@ -5,7 +5,7 @@ stbx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stdbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stwbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 -stfsx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 +stfsx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA,RB,FRS,0,0,0,0 stfdx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stwcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 28400e64..effaa123 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -21,7 +21,7 @@ from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits, insns, MicrOp, In1Sel, In2Sel, In3Sel, - OutSel, CROutSel, + OutSel, CROutSel, LDSTMode, SVP64RMMode, SVP64PredMode, SVP64PredInt, SVP64PredCR) @@ -458,14 +458,30 @@ def get_pdecode_idx_out(dec2, name): OutSel.FRT.value, out, o_isvec) if out_sel == OutSel.FRT.value: return out, o_isvec - print ("get_pdecode_idx_out not found", name) + print ("get_pdecode_idx_out not found", name, out_sel, out, o_isvec) return None, False -# XXX TODO def get_pdecode_idx_out2(dec2, name): + # check first if register is activated for write + out_ok = yield dec2.e.write_ea.ok + if not out_ok: + return None, False + op = dec2.dec.op - print ("TODO: get_pdecode_idx_out2", name) + out_sel = yield op.out_sel + out = yield dec2.e.write_ea.data + o_isvec = yield dec2.o2_isvec + print ("get_pdecode_idx_out2", name, out_sel, out, o_isvec) + if name == 'RA': + if hasattr(op, "upd"): + # update mode LD/ST uses read-reg A also as an output + upd = yield op.upd + print ("get_pdecode_idx_out2", upd, LDSTMode.update.value, + out_sel, OutSel.RA.value, + out, o_isvec) + if upd == LDSTMode.update.value: + return out, o_isvec return None, False @@ -1086,6 +1102,9 @@ class ISACaller: # doing this is not part of svp64, it's because output # registers, to be modified, need to be in the namespace. regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name) + if regnum is None: + regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2, + name) # in case getting the register number is needed, _RA, _RB regname = "_" + name @@ -1192,6 +1211,9 @@ class ISACaller: else: regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name) + if regnum is None: + regnum, is_vec = yield from get_pdecode_idx_out2( + self.dec2, name) if regnum is None: # temporary hack for not having 2nd output regnum = yield getattr(self.decoder, name) diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py index 34d9291c..a6c28611 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fp.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py @@ -22,7 +22,7 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) - def test_sv_fpload(self): + def tst_sv_fpload(self): """>>> lst = ["sv.lfsx 2.v, 0, 0.v" ] """ @@ -57,7 +57,54 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64)) - def test_sv_fpadd(self): + def test_fp_single_ldst(self): + """>>> lst = ["sv.lfsx 0.v, 0, 2.v", # load fp 1/2 from mem 0/8 + "sv.stfsu 0.v, 16(4.v)", # store fp 1/2, update RA *twice* + "sv.lfs 3.v, 0(4.v)", # re-load from UPDATED r4/r5 + ] + """ + lst = SVP64Asm(["sv.lfsx 0.v, 0, 4.v", + "sv.stfsu 0.v, 16(4.v)", + "sv.lfs 3.v, 0(4.v)", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl[0:7] = 2 # VL + svstate.maxvl[0:7] = 2 # MAXVL + print ("SVSTATE", bin(svstate.spr.asint())) + + # memory addresses 0x0000 and 0x0008 + initial_mem = {0x0000: (0x42013333, 8), # 32.3 + 0x0008: (0xC0200000, 8), # -2.5 + 0x0020: (0x1828384822324252, 8), + } + + # and RB will move on from 0 for first iteration to 1 in 2nd + # therefore we must point GPR(4) at initial mem 0x0000 + # and GPR(5) at initial mem 0x0008 + initial_regs = [0] * 32 + initial_regs[4] = 0x0000 # points at memory address 0x0000 (element 0) + initial_regs[5] = 0x0008 # points at memory address 0x0008 (element 1) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, + svstate=svstate, + initial_mem=initial_mem) + print("FPR 1", sim.fpr(0)) + print("FPR 2", sim.fpr(1)) + print("GPR 1", sim.gpr(4)) # should be 0x10 due to update + print("GPR 2", sim.gpr(5)) # should be 0x18 due to update + self.assertEqual(sim.gpr(4), SelectableInt(0x10, 64)) + self.assertEqual(sim.gpr(5), SelectableInt(0x18, 64)) + self.assertEqual(sim.fpr(0), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(1), SelectableInt(0xC004000000000000, 64)) + self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64)) + self.assertEqual(sim.fpr(4), SelectableInt(0xC004000000000000, 64)) + + + def tst_sv_fpadd(self): """>>> lst = ["sv.fadds 6.v, 2.v, 4.v" ] """ diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index 8c3aca32..92142b6e 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -29,7 +29,7 @@ def get_regtype(regname): return "FPR" -def decode_extra(rm, prefix='', verbose=False): +def decode_extra(rm, prefix='', verbose=True): # first turn the svp64 rm into a "by name" dict, recording # which position in the RM EXTRA it goes into # also: record if the src or dest was a CR, for sanity-checking @@ -37,9 +37,9 @@ def decode_extra(rm, prefix='', verbose=False): dest_reg_cr, src_reg_cr = False, False svp64_srcreg_byname = {} svp64_destreg_byname = {} + if verbose: + print ("decode_extra RM", rm) for i in range(4): - if verbose: - print (rm) rfield = rm[prefix+str(i)] if not rfield or rfield == '0': continue diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index e169329c..af1f3883 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -146,7 +146,6 @@ class SVP64Asm: def __init__(self, lst, bigendian=False): self.lst = lst self.trans = self.translate(lst) - self.verbose = False assert bigendian == False, "error, bigendian not supported yet" def __iter__(self): @@ -162,8 +161,7 @@ class SVP64Asm: # now find opcode fields fields = ''.join(ls[1:]).split(',') fields = list(map(str.strip, fields)) - if self.verbose: - print ("opcode, fields", ls, opcode, fields) + print ("opcode, fields", ls, opcode, fields) # sigh have to do setvl here manually for now... if opcode in ["setvl", "setvl."]: @@ -177,8 +175,7 @@ class SVP64Asm: insn |= 0b00000 << (31-30) # XO , bits 26..30 if opcode == 'setvl.': insn |= 1 << (31-31) # Rc=1 , bit 31 - if self.verbose: - print ("setvl", bin(insn)) + print ("setvl", bin(insn)) yield ".long 0x%x" % insn continue @@ -204,10 +201,9 @@ class SVP64Asm: (v30b_op, insn)) v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB" rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV - if self.verbose: - print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '') - print ("v3.0B regs", opcode, v30b_regs) - print (rm) + print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '') + print ("v3.0B regs", opcode, v30b_regs) + print ("RM", rm) # right. the first thing to do is identify the ordering of # the registers, by name. the EXTRA2/3 ordering is in @@ -221,12 +217,9 @@ class SVP64Asm: # (elwidth overrides on CRs are banned) decode = decode_extra(rm) dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode - svp64_reg_byname = {} - svp64_reg_byname.update(svp64_src) - svp64_reg_byname.update(svp64_dest) - if self.verbose: - print ("EXTRA field index, by regname", svp64_reg_byname) + print ("EXTRA field index, src", svp64_src) + print ("EXTRA field index, dest", svp64_dest) # okaaay now we identify the field value (opcode N,N,N) with # the pseudo-code info (opcode RT, RA, RB) @@ -239,11 +232,19 @@ class SVP64Asm: extras = OrderedDict() for idx, (field, regname) in enumerate(opregfields): imm, regname = decode_imm(regname) - extra = svp64_reg_byname.get(regname, None) rtype = get_regtype(regname) - extras[extra] = (idx, field, regname, rtype, imm) - if self.verbose: - print (" ", extra, extras[extra]) + print (" idx find", idx, field, regname, imm) + extra = svp64_src.get(regname, None) + if extra is not None: + extra = ('s', extra, False) + extras[extra] = (idx, field, regname, rtype, imm) + print (" idx src", idx, extra, extras[extra]) + dextra = svp64_dest.get(regname, None) + print ("regname in", regname, dextra) + if dextra is not None: + dextra = ('d', dextra, extra is not None) + extras[dextra] = (idx, field, regname, rtype, imm) + print (" idx dst", idx, extra, extras[dextra]) # great! got the extra fields in their associated positions: # also we know the register type. now to create the EXTRA encodings @@ -263,9 +264,8 @@ class SVP64Asm: immed, field = field[:-1].split("(") field, regmode = decode_reg(field) - if self.verbose: - print (" ", extra_idx, rname, rtype, - regmode, iname, field, end=" ") + print (" ", extra_idx, rname, rtype, + regmode, iname, field, end=" ") # see Mode field https://libre-soc.org/openpower/sv/svp64/ # XXX TODO: the following is a bit of a laborious repeated @@ -289,8 +289,9 @@ class SVP64Asm: else: # range is r0-r127 in increments of 4 assert sv_extra & 0b01 == 0, \ - "vector field %s cannot fit into EXTRA2 %s" % \ - (rname, str(extras[extra_idx])) + "%s: vector field %s cannot fit " \ + "into EXTRA2 %s" % \ + (insn, rname, str(extras[extra_idx])) # all good: encode as vector (bit 2 set) sv_extra = 0b10 | (sv_extra >> 1) elif regmode == 'vector': @@ -375,19 +376,20 @@ class SVP64Asm: field = (field << 2) | cr_subfield # capture the extra field info - if self.verbose: - print ("=>", "%5s" % bin(sv_extra), field) + print ("=>", "%5s" % bin(sv_extra), field) extras[extra_idx] = sv_extra # append altered field value to v3.0b, differs for LDST + srcdest, idx, duplicate = extra_idx + if duplicate: # skip adding to v3.0b fields, already added + continue if ldst_imm: v30b_newfields.append(("%s(%s)" % (immed, str(field)))) else: v30b_newfields.append(str(field)) - if self.verbose: - print ("new v3.0B fields", v30b_op, v30b_newfields) - print ("extras", extras) + print ("new v3.0B fields", v30b_op, v30b_newfields) + print ("extras", extras) # rright. now we have all the info. start creating SVP64 RM svp64_rm = SVP64RMFields() @@ -395,6 +397,8 @@ class SVP64Asm: # begin with EXTRA fields for idx, sv_extra in extras.items(): if idx is None: continue + print (idx) + srcdest, idx, duplicate = idx if etype == 'EXTRA2': svp64_rm.extra2[idx].eq( SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE)) @@ -624,27 +628,24 @@ class SVP64Asm: # nice debug printout. (and now for something completely different) # https://youtu.be/u0WOIwlXE9g?t=146 svp64_rm_value = svp64_rm.spr.value - if self.verbose: - print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value)) - print (" mmode 0 :", bin(mmode)) - print (" pmask 1-3 :", bin(pmask)) - print (" dstwid 4-5 :", bin(destwid)) - print (" srcwid 6-7 :", bin(srcwid)) - print (" subvl 8-9 :", bin(subvl)) - print (" mode 19-23:", bin(mode)) + print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value)) + print (" mmode 0 :", bin(mmode)) + print (" pmask 1-3 :", bin(pmask)) + print (" dstwid 4-5 :", bin(destwid)) + print (" srcwid 6-7 :", bin(srcwid)) + print (" subvl 8-9 :", bin(subvl)) + print (" mode 19-23:", bin(mode)) offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits for idx, sv_extra in extras.items(): if idx is None: continue + srcdest, idx, duplicate = idx start = (10+idx*offs) end = start + offs-1 - if self.verbose: - print (" extra%d %2d-%2d:" % (idx, start, end), - bin(sv_extra)) + print (" extra%d %2d-%2d:" % (idx, start, end), + bin(sv_extra)) if ptype == '2P': - if self.verbose: - print (" smask 16-17:", bin(smask)) - if self.verbose: - print () + print (" smask 16-17:", bin(smask)) + print () # first, construct the prefix from its subfields svp64_prefix = SVP64PrefixFields() @@ -656,8 +657,7 @@ class SVP64Asm: rc = '.' if rc_mode else '' yield ".long 0x%x" % svp64_prefix.insn.value yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields)) - if self.verbose: - print ("new v3.0B fields", v30b_op, v30b_newfields) + print ("new v3.0B fields", v30b_op, v30b_newfields) if __name__ == '__main__': lst = ['slw 3, 1, 4', @@ -681,6 +681,9 @@ if __name__ == '__main__': 'sv.ld 5.v, 4(1.v)', 'setvl. 2, 3, 4, 1, 1', ] + lst = [ + "sv.stfsu 0.v, 16(4.v)", + ] isa = SVP64Asm(lst) print ("list", list(isa)) csvs = SVP64RM()