From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Fri, 4 Jun 2021 19:12:29 +0000 (+0200)
Subject: Updated experiments12 for the latest Coriolis.
X-Git-Tag: LS180_RC3~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f73dc23b438084fd3a0a34e25def7c5ddda3e49;p=soclayout.git

Updated experiments12 for the latest Coriolis.

* To serve as a test bench for the reamining diode insertion
  problems.
---

diff --git a/experiments12/Makefile b/experiments12/Makefile
index 14863fc..35b67be 100755
--- a/experiments12/Makefile
+++ b/experiments12/Makefile
@@ -12,7 +12,7 @@
 
                 VST_FLAGS = --vst-no-lowercase
             YOSYS_FLATTEN =
-         YOSYS_BLACKBOXES = SPBlock_512W64B8W
+         YOSYS_BLACKBOXES = spblock_512w64b8w
                  NETLISTS = $(shell cat netlists.txt)
 
 
@@ -21,11 +21,4 @@
 
 blif:      memory.blif
 vst:       memory.vst
-
-lvx:       lvx-chip_cts_r
-druc:      druc-chip_cts_r
-dreal:     dreal-chip_cts_r
-flatph:    flatph-chip_cts_r
-view:      cgt-chip_cts_r
-layout:    chip_cts_r.ap
 gds:       chip_cts_r.gds
diff --git a/experiments12/SPBlock_512W64B8W.v b/experiments12/SPBlock_512W64B8W.v
deleted file mode 100644
index ddab968..0000000
--- a/experiments12/SPBlock_512W64B8W.v
+++ /dev/null
@@ -1,7 +0,0 @@
-(* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a,
-			 input [63:0] d,
-			 output [63:0] q,
-			 input [7:0] we,
-			 input clk);
-endmodule // SPBlock_512W64B8W
diff --git a/experiments12/SPBlock_512W64B8W.vbe b/experiments12/SPBlock_512W64B8W.vbe
deleted file mode 100644
index c752468..0000000
--- a/experiments12/SPBlock_512W64B8W.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-
--- Phony VHDL interface for SRAM block.
-
-entity SPBlock_512W64B8W is
-   port ( clk     : in  bit
-        ; we      : in  bit_vector( 7 downto 0)
-        ; a       : in  bit_vector( 8 downto 0)
-        ; d       : in  bit_vector(63 downto 0)
-        ; q       : out bit_vector(63 downto 0)
-        ; vdd     : in  bit
-        ; vss     : in  bit
-        );
-end SPBlock_512W64B8W;
-
-architecture behavioral of SPBlock_512W64B8W is
-
-begin
-
-end behavioral;
diff --git a/experiments12/doDesign.py b/experiments12/doDesign.py
index 8df8190..c7eea1d 100644
--- a/experiments12/doDesign.py
+++ b/experiments12/doDesign.py
@@ -10,7 +10,8 @@ from   helpers         import trace, l, u, n
 from   helpers.io      import ErrorMessage, WarningMessage
 from   helpers.overlay import UpdateSession
 import plugins
-from   Hurricane  import Breakpoint, DbU, Point, Box, Transformation, Instance
+from   Hurricane  import Breakpoint, DbU, Point, Box, Transformation, Instance, \
+                         DataBase
 from   plugins.alpha.macro.macro          import Macro
 from   plugins.alpha.block.block          import Block
 from   plugins.alpha.block.configuration  import IoPin, GaugeConf
@@ -123,18 +124,18 @@ def scriptMain ( **kw ):
             chipBuilder = Chip( memoryConf )
             chipBuilder.doChipFloorplan()
             with UpdateSession():
-                sramName = 'subckt_500_SPBlock_512W64B8W'
-                sram     = cell.getInstance( sramName )
+                sramName = 'spblock_512w64b8w'
+                sram     = DataBase.getDB().getCell( 'spblock_512w64b8w' )
                 if not sram:
-                    print( '[ERROR] SRAM instance "{}" not found.'.format(sramName) )
+                    print( '[ERROR] SRAM cell "{}" not found.'.format(sramName) )
                 else:
                     sliceHeight = memoryToChip.conf.sliceHeight
                     coreAb      = cell.getAbutmentBox()
-                    sramAb      = sram.getMasterCell().getAbutmentBox()
+                    sramAb      = sram.getAbutmentBox()
                     position    = Transformation( coreAb.getXMax() - sramAb.getWidth() - 2*sliceHeight
                                                 , u(0.0)
                                                 , Transformation.Orientation.ID )
-                    chipBuilder.placeMacro( 'subckt_500_SPBlock_512W64B8W', position )
+                    chipBuilder.placeMacro( 'spblock_512w64b8w', position )
                     memoryConf.placeArea = Box( coreAb.getXMin()
                                               , coreAb.getYMax() - sliceHeight*26
                                               , coreAb.getXMin() + sliceHeight*25
diff --git a/experiments12/memory.py b/experiments12/memory.py
index 565d179..fb465ee 100644
--- a/experiments12/memory.py
+++ b/experiments12/memory.py
@@ -18,7 +18,7 @@ class ADD(Elaboratable):
         a = Signal(9)
         q = Signal(64) # output
         d = Signal(64) # input
-        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
+        sram = Instance("spblock_512w64b8w", i_a=a, o_q=q, i_d=d,
                                              i_we=self.we, i_clk=ClockSignal())
         m.submodules += sram
 
diff --git a/experiments12/spblock_512w64b8w.v b/experiments12/spblock_512w64b8w.v
new file mode 100644
index 0000000..cd6b9c8
--- /dev/null
+++ b/experiments12/spblock_512w64b8w.v
@@ -0,0 +1,7 @@
+(* blackbox = 1 *)
+module spblock_512w64b8w(input [8:0] a,
+			 input [63:0] d,
+			 output [63:0] q,
+			 input [7:0] we,
+			 input clk);
+endmodule // SPBlock_512W64B8W
diff --git a/experiments12/spblock_512w64b8w.vbe b/experiments12/spblock_512w64b8w.vbe
new file mode 100644
index 0000000..553f462
--- /dev/null
+++ b/experiments12/spblock_512w64b8w.vbe
@@ -0,0 +1,19 @@
+
+-- Phony VHDL interface for SRAM block.
+
+entity spblock_512w64b8w is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock_512w64b8w;
+
+architecture behavioral of spblock_512w64b8w is
+
+begin
+
+end behavioral;