From: Luke Kenneth Casson Leighton Date: Wed, 14 Jul 2021 18:29:49 +0000 (+0100) Subject: subtract one from SVi field for setvl assembler X-Git-Tag: xlen-bcd~289 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f78d59de50f4f830f3d7dc5a82355d7ade981ff;p=openpower-isa.git subtract one from SVi field for setvl assembler update all uses to match --- diff --git a/media/audio/mp3/mp3_0_apply_window_float_basicsv.s b/media/audio/mp3/mp3_0_apply_window_float_basicsv.s index ebbdedb2..38888524 100644 --- a/media/audio/mp3/mp3_0_apply_window_float_basicsv.s +++ b/media/audio/mp3/mp3_0_apply_window_float_basicsv.s @@ -53,7 +53,7 @@ ff_mpadsp_apply_window_float_sv: add out2, out, 0 # set Vector Length - setvl 0, 0, 7, 1, 1, 0# setvli MVL=8, VL=8 + setvl 0, 0, 8, 1, 1, 0# setvli MVL=8, VL=8 addi win2, win, 124 # w2 = window + 31 lfiwax sum, 0, 5 # sum = *dither_state diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 8cbd8174..369d269f 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -24,9 +24,9 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) def test_svstep_1(self): - lst = SVP64Asm(["setvl 0, 0, 9, 1, 1, 1", # actual setvl (VF mode) - "setvl 0, 0, 0, 1, 0, 0", # svstep - "setvl 0, 0, 0, 1, 0, 0" # svstep + lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode) + "setvl 0, 0, 1, 1, 0, 0", # svstep + "setvl 0, 0, 1, 1, 0, 0" # svstep ]) lst = list(lst) @@ -55,9 +55,9 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_2(self): """tests svstep when it reaches VL """ - lst = SVP64Asm(["setvl 0, 0, 1, 1, 1, 1", # actual setvl (VF mode) - "setvl. 0, 0, 0, 1, 0, 0", # svstep (Rc=1) - "setvl. 0, 0, 0, 1, 0, 0" # svstep (Rc=1) + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode) + "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1) + "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1) ]) lst = list(lst) @@ -93,9 +93,9 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_3(self): """tests svstep when it *doesn't* reach VL """ - lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode) - "setvl. 0, 0, 0, 1, 0, 0", # svstep (Rc=1) - "setvl. 0, 0, 0, 1, 0, 0" # svstep (Rc=1) + lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1", # actual setvl (VF mode) + "setvl. 0, 0, 1, 1, 0, 0", # svstep (Rc=1) + "setvl. 0, 0, 1, 1, 0, 0" # svstep (Rc=1) ]) lst = list(lst) @@ -132,7 +132,7 @@ class DecoderTestCase(FHDLTestCase): def test_setvl_1(self): """straight setvl, testing if VL and MVL are over-ridden """ - lst = SVP64Asm(["setvl 1, 0, 9, 0, 1, 1", + lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1", ]) lst = list(lst) @@ -158,7 +158,7 @@ class DecoderTestCase(FHDLTestCase): * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 """ - isa = SVP64Asm(["setvl 3, 0, 1, 0, 1, 1", + isa = SVP64Asm(["setvl 3, 0, 2, 0, 1, 1", 'sv.add 1.v, 5.v, 9.v' ]) lst = list(isa) @@ -183,11 +183,11 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_add_1(self): """tests svstep with an add, when it reaches VL - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0" + "setvl. 0, 0, 1, 1, 0, 0" ]) sequence is as follows: * setvl sets VL=2 but also "Vertical First" mode. @@ -199,11 +199,11 @@ class DecoderTestCase(FHDLTestCase): which now equals VL. srcstep and dststep are both set to zero, and MSR[SVF] is cleared. """ - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0", # svstep + "setvl. 0, 0, 1, 1, 0, 0", # svstep 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0" # svstep + "setvl. 0, 0, 1, 1, 0, 0" # svstep ]) lst = list(lst) @@ -252,9 +252,9 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_add_2(self): """tests svstep with a branch. - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -0xc" ]) sequence is as follows: @@ -278,9 +278,9 @@ class DecoderTestCase(FHDLTestCase): first, then looping back and running all element 1, then all element 2 etc. """ - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 0, 1, 0, 0", # svstep - this is 64-bit! + "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit! "bc 4, 2, -0xc" # branch to add (64-bit op so -0xc!) ]) lst = list(lst) diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index 27d3a70f..0c5d23a1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -197,7 +197,7 @@ class FFTTestCase(FHDLTestCase): "svshape 8, 1, 1, 1, 1", "svremap 31, 1, 0, 2, 0, 1", "sv.ffmadds 0.v, 0.v, 0.v, 8.v", - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -16" ]) runs a full in-place O(N log2 N) butterfly schedule for @@ -212,7 +212,7 @@ class FFTTestCase(FHDLTestCase): "svshape 8, 1, 1, 1, 1", "svremap 31, 1, 0, 2, 0, 1", "sv.ffmadds 0.v, 0.v, 0.v, 8.v", - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -16" ]) lst = list(lst) @@ -284,7 +284,7 @@ class FFTTestCase(FHDLTestCase): # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1) "svremap 26, 0, 0, 0, 0, 1", "sv.ffadds 0.v, 24, 0.v", - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -28" ]) @@ -316,7 +316,7 @@ class FFTTestCase(FHDLTestCase): # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1) "svremap 26, 0, 0, 0, 0, 1", "sv.ffadds 0.v, 24, 0.v", - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -28" ]) lst = list(lst) @@ -534,7 +534,7 @@ class FFTTestCase(FHDLTestCase): "sv.ffadds 8.v, 26, 8.v", # vh/vl +- tpim # svstep loop - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", "bc 4, 2, -84" ]) lst = list(lst) diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index 43c9cda6..565480cf 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -65,13 +65,13 @@ class SVSTATETestCase(FHDLTestCase): def test_svstep_add_1(self): """tests svstep with an add, using scalar adds, when it reaches VL - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1, 5.v, 9.v', 'sv.addi 12.v, 1, 1', - "setvl. 0, 0, 0, 1, 0, 0", + "setvl. 0, 0, 1, 1, 0, 0", 'sv.add 1, 5.v, 9.v', 'sv.addi 12.v, 1, 1', - "setvl. 0, 0, 0, 1, 0, 0" + "setvl. 0, 0, 1, 1, 0, 0" ]) sequence is as follows: @@ -96,13 +96,13 @@ class SVSTATETestCase(FHDLTestCase): store the result in r13 (0x3335). """ - lst = SVP64Asm(["setvl 3, 0, 1, 1, 1, 1", + lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1, 5.v, 9.v', # scalar dest (into r1) 'sv.addi 12.v, 1, 1', # scalar src (from r1) - "setvl. 0, 0, 0, 1, 0, 0", # svstep + "setvl. 0, 0, 1, 1, 0, 0", # svstep 'sv.add 1, 5.v, 9.v', # again, scalar dest 'sv.addi 12.v, 1, 1', # but vector dest - "setvl. 0, 0, 0, 1, 0, 0" # svstep + "setvl. 0, 0, 1, 1, 0, 0" # svstep ]) lst = list(lst) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 05c768fd..b36ae321 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -181,12 +181,13 @@ class SVP64Asm: log ("opcode, fields substed", ls, opcode, fields) # sigh have to do setvl here manually for now... + # note the subtract one from SVi. if opcode in ["setvl", "setvl."]: insn = 22 << (31-5) # opcode 22, bits 0-5 fields = list(map(int, fields)) insn |= fields[0] << (31-10) # RT , bits 6-10 insn |= fields[1] << (31-15) # RA , bits 11-15 - insn |= fields[2] << (31-22) # SVi , bits 16-22 + insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22 insn |= fields[3] << (31-25) # ms , bit 25 insn |= fields[4] << (31-24) # vs , bit 24 insn |= fields[5] << (31-23) # vf , bit 23