From: Andreas Sandberg <andreas.sandberg@arm.com>
Date: Tue, 2 May 2017 16:26:34 +0000 (+0100)
Subject: arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU
X-Git-Tag: v19.0.0.0~2777
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f835d88a337c74869393b76ef3c398c324754cc;p=gem5.git

arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU

The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.

Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
---

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 39530702c..ac2f4759f 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -163,7 +163,7 @@ PMU::setMiscReg(int misc_reg, MiscReg val)
         return;
 
       case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
-        setCounterTypeRegister(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
+        setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
         return;
 
       case MISCREG_PMCCFILTR: