From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Thu, 19 Aug 2021 17:50:17 +0000 (+0000)
Subject: test_caller_bcd: make bit changes more VHDL-like
X-Git-Tag: xlen-bcd~111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f9a6b3eb3856eae4af40ca9c29d89effc349e47;p=openpower-isa.git

test_caller_bcd: make bit changes more VHDL-like
---

diff --git a/src/openpower/decoder/isa/test_caller_bcd.py b/src/openpower/decoder/isa/test_caller_bcd.py
index 6ce0a065..50141cbe 100644
--- a/src/openpower/decoder/isa/test_caller_bcd.py
+++ b/src/openpower/decoder/isa/test_caller_bcd.py
@@ -330,15 +330,9 @@ class BCDTestCase(FHDLTestCase):
                 lo = i * 4
                 hi = (i + 1) * 4
                 if (a_in[hi] ^ b_in[hi] ^ (sum_with_carry[hi] == 0)):
-                    addg6s[lo + 3] = 0
-                    addg6s[lo + 2] = 1
-                    addg6s[lo + 1] = 1
-                    addg6s[lo + 0] = 0
+                    addg6s[lo:lo + 3 + 1] = [0, 1, 1, 0]
             if sum_with_carry[64] == 0:
-                addg6s[63] = 0
-                addg6s[62] = 1
-                addg6s[61] = 1
-                addg6s[60] = 0
+                addg6s[60:63] = [0, 1, 1, 0]
             return int("".join(map(str, reversed(addg6s))), 2)
 
         bcd = [f"{digit:04b}" for digit in range(10)]