From: lkcl <lkcl@web>
Date: Fri, 10 Nov 2023 07:24:58 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fb2ed584c80a671f71bc8ffbac77752ea56bbd5;p=libreriscv.git

---

diff --git a/openpower/sv/cookbook/remap_matrix.mdwn b/openpower/sv/cookbook/remap_matrix.mdwn
index 8eefea51e..680801e39 100644
--- a/openpower/sv/cookbook/remap_matrix.mdwn
+++ b/openpower/sv/cookbook/remap_matrix.mdwn
@@ -351,25 +351,26 @@ of the consecutive instruction/s (depending on if REMAP is set to persistent).
 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
 
 ```
-    svremap 31, 1, 2, 3, 0, 0, 0
+    svremap 15, 1, 2, 3, 0, 0, 0
 ```
 
 breakdown:
 
 - `SVme=31`, 5-bit bitmask determines which registers have REMAP applied.
-Bitfields are: `RA|RB|RC|RT|EA/FRS` In this example, all input registers
+Bitfields are: `RA|RB|RC|RT|EA` In this example, all input registers
 (RA, RB, RC) of *any* scalar instruction to follow and output register (RT)
-will have REMAP applied.
-- `mix/mox` fields determine which shape is applied to the activated register
+will have REMAP applied, but the 2nd output register will not.
+- `mi{N}/mo{N}` fields determine which shape is applied to the activated register
 - `mi0=1`, instruction operand RA has SVSHAPE1 applied to it.
 - `mi1=2`, instruction operand RB has SVSHAPE2 applied to it.
 - `mi2=3`, instruction operand RC has SVSHAPE3 applied to it.
 - `mo0=0`, instruction result RT has SVSHAPE0 applied to it.
-- `mo1=0`, instruction result EA/FRS has SVSHAPE0 applied to it.
+- `mo1=0`, instruction result EA/FRS does **not** have SVSHAPE0 applied to it
 *(not applicable for this example)*
 - `pst=0`, if set, REMAP remains enabled until explicitly disabled, or another
 REMAP, or setvl is setup.
 
+Thus the link between the *shapes* and the *actual registers* is established.
 
 ## maddld - Multiply-Add Low Doubleword VA-form
 
@@ -380,7 +381,7 @@ third operand to be the same as the result register, which functions as
 an accumulator.
 
 ```
-    sv.maddld *0, *16, *32, *0
+sv.maddld *0, *16, *32, *0
 ```
 
 breakdown:
@@ -398,9 +399,11 @@ multiply-add accumulate behaviour.
 - Set up the LibreSOC development environment (need to have openpower-isa repo
 setup and installed).
 
+```
     $: cd /PATH/TO/src/openpower-isa/src/openpower/decoder/isa/
     $: python3 test_caller_svp64_matrix.py >& /tmp/f
-
+```
+qq
 (All test cases are enabled by default; extra test cases can be disabled by changing
 `test_` to `tst_` or any other prefix.)