From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 8 Oct 2019 19:41:26 +0000 (-0700)
Subject: Revert "Add test that is expecting to fail"
X-Git-Tag: working-ls180~998
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fb604c75d3e8ee45d35fac8b787cb95a8adcf84;p=yosys.git

Revert "Add test that is expecting to fail"

This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
---

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 1627a37e3..2079d2f34 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -2,23 +2,3 @@ read_verilog -sv initval.v
 proc;;
 
 sat -seq 10 -prove-asserts
-
-read_verilog <<EOT
-module gold(input clk, input i, output reg [1:0] o);
-initial o = 2'b10;
-always @(posedge clk)
-   o[0] <= {i,i};
-endmodule
-
-module gate(input clk, input i, output reg [1:0] o);
-initial o = 2'b10;
-always @(posedge clk)
-   o[0] <= i;
-always @*
-   o[1] <= o[0];
-endmodule
-EOT
-
-proc
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 1 -falsify -prove-asserts -show-ports miter