From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 17:45:09 +0000 (+0100)
Subject: rename nia_out to nia, clarify with variables in main_stage branch
X-Git-Tag: div_pipeline~1100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fbd35a79c34855b7d19176c239fb7eff2edc24f;p=soc.git

rename nia_out to nia, clarify with variables in main_stage branch
---

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index d1dfbbda..99998a1d 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -34,7 +34,7 @@ class BranchMainStage(PipeModBase):
         comb = m.d.comb
         op = self.i.ctx.op
         lk = op.lk # see PowerDecode2 as to why this is done
-        nia_out, lr = self.o.nia_out, self.o.lr
+        nia_o, lr_o = self.o.nia, self.o.lr
 
         # obtain relevant instruction fields
         i_fields = self.fields.FormI
@@ -101,16 +101,16 @@ class BranchMainStage(PipeModBase):
 
         ###### output next instruction address #####
 
-        comb += nia_out.data.eq(br_addr)
-        comb += nia_out.ok.eq(br_taken)
+        comb += nia_o.data.eq(br_addr)
+        comb += nia_o.ok.eq(br_taken)
 
         ###### link register - only activate on operations marked as "lk" #####
 
         with m.If(lk):
             # ctx.op.lk is the AND of the insn LK field *and* whether the
             # op is to "listen" to the link field
-            comb += lr.data.eq(self.i.cia + 4)
-            comb += lr.ok.eq(1)
+            comb += lr_o.data.eq(self.i.cia + 4)
+            comb += lr_o.ok.eq(1)
 
         ###### and context #####
         comb += self.o.ctx.eq(self.i.ctx)
diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index 5f7a3fdd..4ace13dd 100644
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -186,11 +186,11 @@ class TestRunner(FHDLTestCase):
             sim.run()
 
     def assert_outputs(self, branch, dec2, sim, prev_nia):
-        branch_taken = yield branch.n.data_o.nia_out.ok
+        branch_taken = yield branch.n.data_o.nia.ok
         sim_branch_taken = prev_nia != sim.pc.CIA
         self.assertEqual(branch_taken, sim_branch_taken)
         if branch_taken:
-            branch_addr = yield branch.n.data_o.nia_out.data
+            branch_addr = yield branch.n.data_o.nia.data
             self.assertEqual(branch_addr, sim.pc.CIA.value)
 
         lk = yield dec2.e.lk