From: Malek Musleh <malek.musleh@gmail.com>
Date: Fri, 28 Sep 2012 13:35:25 +0000 (-0400)
Subject: Configs: SE script fix for Alpha and Ruby simulations
X-Git-Tag: stable_2013_06_16~374
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fc23b9b96769b8274e93f5cf14bb29b0ba044f0;p=gem5.git

Configs: SE script fix for Alpha and Ruby simulations

PIO interrupt port is only present for x86. Do not attempt to connect
for other ISAs.
---

diff --git a/configs/example/se.py b/configs/example/se.py
index b60baf041..adebab1e2 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -190,15 +190,17 @@ if options.ruby:
         ruby_port = system.ruby._cpu_ruby_ports[i]
 
         # Create the interrupt controller and connect its ports to Ruby
+        # Note that the interrupt controller is always present but only
+        # in x86 does it have message ports that need to be connected
         system.cpu[i].createInterruptController()
-        system.cpu[i].interrupts.pio = ruby_port.master
-        system.cpu[i].interrupts.int_master = ruby_port.slave
-        system.cpu[i].interrupts.int_slave = ruby_port.master
 
         # Connect the cpu's cache ports to Ruby
         system.cpu[i].icache_port = ruby_port.slave
         system.cpu[i].dcache_port = ruby_port.slave
         if buildEnv['TARGET_ISA'] == 'x86':
+            system.cpu[i].interrupts.pio = ruby_port.master
+            system.cpu[i].interrupts.int_master = ruby_port.slave
+            system.cpu[i].interrupts.int_slave = ruby_port.master
             system.cpu[i].itb.walker.port = ruby_port.slave
             system.cpu[i].dtb.walker.port = ruby_port.slave
 else: