From: lkcl <lkcl@web>
Date: Sun, 13 Dec 2020 23:00:41 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fc8030e55be5678a0f83baa50fa3be179f08ee2;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 0d524d0e4..57a5ad1fe 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -17,7 +17,7 @@ Advantages of these design principles:
 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
 * Completely wipes not just SIMD opcode proliferation off the
-  map but off of Vectorisation as well.  No more separate Vector
+  map but off of Vectorisation ISAs as well.  No more separate Vector
   instructions.
 
 Pages being developed and examples