From: lkcl <lkcl@web>
Date: Tue, 14 Jul 2020 19:36:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2351
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fcd305da3f0c8ec5c960b3516d0a9db242b9aea;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 4ea2234d9..0988b42e2 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -8,8 +8,9 @@ A minimum of 4 register files are required for POWER:
 
 * Floating-point
 * Integer
-* Control and Condition Code Registers (CR0-7, CTR, LR)
+* Control and Condition Code Registers (CR0-7)
 * SPRs (Special Purpose Registers)
+* Fast Registers (PC, MSR, CTR, LR, SRR0, SRR1 etc.)
 
 Source code: