From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 12:53:05 +0000 (+0100)
Subject: make vlen loop run times subvl, set subvl default to 1 not 0
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fda13c559be78dbb69c9cb0d353e4856a62fde6;p=riscv-isa-sim.git

make vlen loop run times subvl, set subvl default to 1 not 0
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index a8dacd3..f249d7e 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -46,7 +46,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   // in a stack of other things that are needed.
   insn_bits_t bits = s_insn.bits();
   int vlen = 0;
-  int subvl = 0;
+  int subvl = 1;
   if (p->get_state()->prv == 0) { // XXX HACK - disable in supervisor mode
     vlen = p->get_state()->sv().vl;
     subvl = p->get_state()->sv().subvl;
@@ -98,10 +98,11 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_spec_t sp = {0, NULL};
   if (vlen > 0)
   {
-    fprintf(stderr, "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d\n",
+    fprintf(stderr,
+            "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d subvl %d\n",
             xstr(INSN), INSNCODE, p->get_state()->prv,
             s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
-            vlen);
+            vlen, subvl);
 #ifdef INSN_TYPE_C_STACK_LD
     sp = insn._remap(X_SP, true, src_offs, src_subo);
 #endif
@@ -155,7 +156,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   {
     vlen = 1; // minimum of one loop
   }
-  for (int voffs=0; voffs < vlen; voffs++)
+  for (int voffs=0; voffs < vlen*subvl; voffs++)
   {
     insn.reset_vloop_check();
 #ifdef INSN_C_MV
@@ -213,7 +214,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                       "vlen %d stop %d pred %lx rdv %lx v %ld rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2()),
+                dest_pred & (1<<(voffs/subvl)), READ_REG(insn._rvc_rs2()),
                 insn._rvc_rs2().reg, insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
 #ifdef INSN_C_LWSP
@@ -221,7 +222,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                       "vlen %d stop %d pred %lx rdv %lx rd %ld rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rd()),
+                dest_pred & (1<<(voffs/subvl)), READ_REG(insn._rd()),
                 insn._rd().reg, insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
 #ifdef INSN_C_BEQZ
@@ -229,7 +230,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                       "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %ld\n",
                 xstr(INSN), INSNCODE, voffs, _target_reg, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s()),
+                dest_pred & (1<<(voffs/subvl)), READ_REG(insn._rvc_rs1s()),
                 insn._rvc_rs1s().reg);
 #endif
 #ifdef INSN_LD
@@ -237,7 +238,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                       "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %ld\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rs1()),
+                dest_pred & (1<<(voffs/subvl)), READ_REG(insn._rs1()),
                 insn._rs1().reg);
 #endif
       #include INCLUDEFILE
@@ -269,14 +270,16 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
       if (vlen > 1)
       {
 #if defined(USING_REG_RD)
-        fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
+        fprintf(stderr,
+                "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rd()));
+                dest_pred & (1<<(voffs/subvl)), READ_REG(insn._rd()));
 #endif
 #if defined(USING_REG_FRD)
-        fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%g\n",
+        fprintf(stderr,
+                "reg %s %x vloop %d vlen %d stop %d pred %lx rd%g\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs),
+                dest_pred & (1<<(voffs/subvl)),
                 (double)(READ_FREG(insn._rd())).v[0]);
 #endif
       }
@@ -288,7 +291,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
       inc_offs(vlen, subvl, *src_offs, *src_subo);
 #endif
       inc_offs(vlen, subvl, *dest_offs, *dest_subo);
-  }
+  } // end voffs loop
 #ifdef INSN_TYPE_BRANCH
   // ok, at the end of the loop, if the predicates are equal,
   // we're good to branch.  use the saved address (to avoid
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 581c549..6338ada 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -551,7 +551,7 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       state.sv().subvl = std::max(1, std::min(4, (int)val));
       old_val = state.sv().subvl;
       // TODO XXX throw exception if val attempted to be set == 0
-      fprintf(stderr, "set VL %lx\n", state.sv().vl);
+      fprintf(stderr, "set SUBVL %lx\n", state.sv().subvl);
       break;
     case CSR_USVVL:
       state.sv().vl = std::min(state.sv().mvl, val + 1);