From: lkcl <lkcl@web>
Date: Mon, 8 May 2023 11:41:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fdbf0687e4f7d43ee3a984f3d6229f89f7d0a3b;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 7ee59bc94..902bd73c2 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -75,12 +75,12 @@ Field result *is* the main result.
 
 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
-|6 | 7 |19-20|  21 | 22   23 |  description     |
-|--|---|-----| --- |---------|----------------- |
-|/ | / |0 RG |   0 | dz  sz  | simple mode                      |
-|/ | / |0 RG |   1 | dz  sz  | scalar reduce mode (mapreduce) |
-|zz|SNZ|1 VLI| inv |  CR-bit | Ffirst 3-bit mode      |
-|/ |SNZ|1 VLI| inv |  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
+|6 | 7 |19-20|21 | 22   23 |  description     |
+|--|---|-----|---|---------|------------------|
+|/ | / |0 RG | 0 | dz  sz  | simple mode                      |
+|/ | / |0 RG | 1 | dz  sz  | scalar reduce mode (mapreduce) |
+|zz|SNZ|1 VLI|inv|  CR-bit | Ffirst 3-bit mode      |
+|/ |SNZ|1 VLI|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
 
 Fields: