From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 24 May 2006 18:31:06 +0000 (-0400)
Subject: Support new flags now used instead of flags in decoder.isa.
X-Git-Tag: m5_2.0_beta1~36^2~108^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fe35232322daef87a0b85d7f3ca4c18330ed7c4;p=gem5.git

Support new flags now used instead of flags in decoder.isa.

cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
    Support new flags added in.

--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
---

diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh
index 15adae9b4..ffbcf3340 100644
--- a/cpu/ozone/front_end_impl.hh
+++ b/cpu/ozone/front_end_impl.hh
@@ -503,11 +503,14 @@ FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
     if (serializeNext) {
         inst->setSerializeBefore();
         serializeNext = false;
-    } else if (!inst->isSerializing()) {
+    } else if (!inst->isSerializing() &&
+               !inst->isIprAccess() &&
+               !inst->isStoreConditional()) {
         return false;
     }
 
-    if (inst->isSerializeBefore() && !inst->isSerializeHandled()) {
+    if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
+        !inst->isSerializeHandled()) {
         DPRINTF(FE, "Serialize before instruction encountered.\n");
 
         if (!inst->isTempSerializeBefore()) {
@@ -523,7 +526,8 @@ FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
 
         barrierInst = inst;
         return true;
-    } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) {
+    } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
+               && !inst->isSerializeHandled()) {
         DPRINTF(FE, "Serialize after instruction encountered.\n");
 
         inst->setSerializeHandled();
diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh
index 881d6e6b1..41b4ea24b 100644
--- a/cpu/ozone/lw_back_end_impl.hh
+++ b/cpu/ozone/lw_back_end_impl.hh
@@ -66,8 +66,9 @@ LWBackEnd<Impl>::wakeDependents(DynInstPtr &inst, bool memory_deps)
         DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
 
         if (dep_inst->readyToIssue() && dep_inst->isInROB() &&
-            !dep_inst->isNonSpeculative() &&
-            dep_inst->memDepReady() && !dep_inst->isMemBarrier() && !dep_inst->isWriteBarrier()) {
+            !dep_inst->isNonSpeculative() && !dep_inst->isStoreConditional() &&
+            dep_inst->memDepReady() && !dep_inst->isMemBarrier() &&
+            !dep_inst->isWriteBarrier()) {
             DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n",
                     dep_inst->seqNum);
             exeList.push(dep_inst);
@@ -768,7 +769,9 @@ LWBackEnd<Impl>::dispatchInsts()
             }
             memBarrier = inst;
             inst->setCanCommit();
-        } else if (inst->readyToIssue() && !inst->isNonSpeculative()) {
+        } else if (inst->readyToIssue() &&
+                   !inst->isNonSpeculative() &&
+                   !inst->isStoreConditional()) {
             if (inst->isMemRef()) {
 
                 LSQ.insert(inst);
@@ -803,7 +806,7 @@ LWBackEnd<Impl>::dispatchInsts()
                 exeList.push(inst);
             }
         } else {
-            if (inst->isNonSpeculative()) {
+            if (inst->isNonSpeculative() || inst->isStoreConditional()) {
                 inst->setCanCommit();
                 DPRINTF(BE, "Adding non speculative instruction\n");
             }
@@ -1079,6 +1082,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
     // or store inst.  Signal backwards that it should be executed.
     if (!inst->isExecuted()) {
         if (inst->isNonSpeculative() ||
+            inst->isStoreConditional() ||
             inst->isMemBarrier() ||
             inst->isWriteBarrier()) {
 #if !FULL_SYSTEM
diff --git a/cpu/ozone/lw_lsq_impl.hh b/cpu/ozone/lw_lsq_impl.hh
index 2f85a0396..f72bbb1cc 100644
--- a/cpu/ozone/lw_lsq_impl.hh
+++ b/cpu/ozone/lw_lsq_impl.hh
@@ -364,10 +364,9 @@ OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
         if (store_fault != NoFault) {
             panic("Fault in a store instruction!");
             storeFaultInst = store_inst;
-        } else if (store_inst->isNonSpeculative()) {
-            // Nonspeculative accesses (namely store conditionals)
-            // need to set themselves as able to writeback if we
-            // haven't had a fault by here.
+        } else if (store_inst->isStoreConditional()) {
+            // Store conditionals need to set themselves as able to
+            // writeback if we haven't had a fault by here.
             (*sq_it).canWB = true;
 
             ++storesToWB;