From: whitequark <whitequark@whitequark.org>
Date: Sun, 21 Feb 2021 20:53:56 +0000 (+0000)
Subject: Merge pull request #2591 from zachjs/verilog-preproc-unapplied
X-Git-Tag: working-ls180~77
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fee43cde0ec424e52ea62f78722b061aaac280a;p=yosys.git

Merge pull request #2591 from zachjs/verilog-preproc-unapplied

verilog: error on macro invocations with missing argument lists
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3fee43cde0ec424e52ea62f78722b061aaac280a