From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 30 Jul 2020 19:37:25 +0000 (+0200)
Subject: cpu/zynq7000: set csr map to 0x00000000.
X-Git-Tag: 24jan2021_ls180~41
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ff1bcaf0526929f9972bb94024cb265a61864af;p=litex.git

cpu/zynq7000: set csr map to 0x00000000.
---

diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py
index 9ed783a8..91d7692e 100644
--- a/litex/soc/cores/cpu/zynq7000/core.py
+++ b/litex/soc/cores/cpu/zynq7000/core.py
@@ -24,6 +24,10 @@ class Zynq7000(CPU):
     nop                  = "nop"
     io_regions           = {0x00000000: 0x100000000} # origin, length
 
+    @property
+    def mem_map(self):
+        return {"csr": 0x00000000}
+
     def __init__(self, platform, variant):
         self.platform       = platform
         self.reset          = Signal()