From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Oct 2013 20:28:42 +0000 (+0200)
Subject: Improved xilinx mojo_counter example
X-Git-Tag: yosys-0.2.0~444
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4007b41d40147bf3d282f25f6c177a17fb2a8f76;p=yosys.git

Improved xilinx mojo_counter example
---

diff --git a/techlibs/xilinx7/example_mojo_counter/example.sh b/techlibs/xilinx7/example_mojo_counter/example.sh
index 17fc650e4..87af0ea31 100644
--- a/techlibs/xilinx7/example_mojo_counter/example.sh
+++ b/techlibs/xilinx7/example_mojo_counter/example.sh
@@ -19,11 +19,14 @@ abc -lut 6; opt
 # map internal cells to FPGA cells
 techmap -map ../cells.v; opt
 
+# insert i/o buffers
+iopadmap -outpad OBUF I:O -inpad BUFGP O:I
+
 # write netlist
 write_edif synth.edif
 EOT
 
-cat > synth.ut <<- EOT
+cat > bitgen.ut <<- EOT
 	-w
 	-g DebugBitstream:No
 	-g Binary:no
diff --git a/techlibs/xilinx7/example_mojo_counter/example.v b/techlibs/xilinx7/example_mojo_counter/example.v
index 1327d9b86..8e79942e2 100644
--- a/techlibs/xilinx7/example_mojo_counter/example.v
+++ b/techlibs/xilinx7/example_mojo_counter/example.v
@@ -7,7 +7,7 @@ output led_3, led_2, led_1, led_0;
 reg [31:0] counter;
 
 always @(posedge clk)
-	counter <= counter + 1;
+	counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
 
 assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;