From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 21:01:54 +0000 (-0700)
Subject: aiger: -xaiger to return $_FF_ flops
X-Git-Tag: working-ls180~549^2~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4017cc6380c3b13f416e55e4e65cf98e7caf45e1;p=yosys.git

aiger: -xaiger to return $_FF_ flops
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 16e94c394..d25587e48 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -787,21 +787,8 @@ void AigerReader::post_process()
 		log_assert(q->port_input);
 		q->port_input = false;
 
-		Cell* ff;
-		int clock_index = mergeability[i];
-		if (clock_index & 1) {
-			ff = module->addCell(NEW_ID, ID($_DFF_N_));
-			clock_index--;
-		}
-		else
-			ff = module->addCell(NEW_ID, ID($_DFF_P_));
-		auto r = mergeability_to_clock.insert(clock_index);
-		if (r.second)
-			r.first->second = module->addWire(NEW_ID);
-		ff->setPort(ID::C, r.first->second);
-		ff->setPort(ID::D, d);
-		ff->setPort(ID::Q, q);
-		log_assert(GetSize(q) == 1);
+		Cell* ff = module->addFfGate(NEW_ID, d, q);
+		ff->attributes[ID::abc9_mergeability] = mergeability[i];
 		q->attributes[ID::init] = initial_state[i];
 	}