From: Luke Kenneth Casson Leighton Date: Sat, 27 Oct 2018 06:07:59 +0000 (+0100) Subject: READ_FREG not to return an alternative type X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=402286cff7881bc3b283cb43e6da23f34642473b;p=riscv-isa-sim.git READ_FREG not to return an alternative type --- diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 1f20354..5c5d628 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -125,7 +125,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value) STATE.XPR.write(reg, wval); } -sv_freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec) +freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec) { reg_t reg = spec.reg; uint8_t elwidth = _insn->reg_elwidth(reg, true); diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index ab484bb..90f2791 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -85,7 +85,7 @@ public: void (WRITE_FRD)(sv_float64_t value); void (WRITE_FRD)(sv_float32_t value); reg_t (READ_REG)(reg_spec_t const& i); - sv_freg_t (READ_FREG)(reg_spec_t const& i); + freg_t (READ_FREG)(reg_spec_t const& i); processor_t *p; sv_insn_t *_insn;