From: Gabe Black Date: Sat, 21 Sep 2019 06:38:12 +0000 (-0700) Subject: fastmodel: Add CortexA76x[234] models. X-Git-Tag: v19.0.0.0~345 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4023d93cc50c1dfba42bb1615ce3e4a61b82098d;p=gem5.git fastmodel: Add CortexA76x[234] models. These use the parameterization added in earlier commits. Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py index ebc5b823d..c1b996e54 100644 --- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py +++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py @@ -364,3 +364,42 @@ class FastModelCortexA76x1(FastModelCortexA76Cluster): cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]) ] evs = FastModelScxEvsCortexA76x1() + +class FastModelScxEvsCortexA76x2(SystemC_ScModule): + type = 'FastModelScxEvsCortexA76x2' + cxx_class = 'FastModel::ScxEvsCortexA76' + cxx_template_params = [ 'class Types' ] + cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh' + +class FastModelCortexA76x2(FastModelCortexA76Cluster): + cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu1' ]) ] + + evs = FastModelScxEvsCortexA76x2() + +class FastModelScxEvsCortexA76x3(SystemC_ScModule): + type = 'FastModelScxEvsCortexA76x3' + cxx_class = 'FastModel::ScxEvsCortexA76' + cxx_template_params = [ 'class Types' ] + cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh' + +class FastModelCortexA76x3(FastModelCortexA76Cluster): + cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu1' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu2' ]) ] + + evs = FastModelScxEvsCortexA76x3() + +class FastModelScxEvsCortexA76x4(SystemC_ScModule): + type = 'FastModelScxEvsCortexA76x4' + cxx_class = 'FastModel::ScxEvsCortexA76' + cxx_template_params = [ 'class Types' ] + cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh' + +class FastModelCortexA76x4(FastModelCortexA76Cluster): + cores = [ FastModelCortexA76(thread_paths=[ 'core.cpu0' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu1' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu2' ]), + FastModelCortexA76(thread_paths=[ 'core.cpu3' ]) ] + + evs = FastModelScxEvsCortexA76x4() diff --git a/src/arch/arm/fastmodel/CortexA76/SConscript b/src/arch/arm/fastmodel/CortexA76/SConscript index f719874c4..de4fae893 100644 --- a/src/arch/arm/fastmodel/CortexA76/SConscript +++ b/src/arch/arm/fastmodel/CortexA76/SConscript @@ -32,11 +32,13 @@ if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm': protocol_dir = Dir('..').Dir('protocol') -ArmFastModelComponent(File('x1.sgproj'), - File('x1.lisa'), - protocol_dir.File( - 'ExportedClockRateControlProtocol.lisa') - ).prepare_env(env) +for name in ('x1', 'x2', 'x3', 'x4'): + ArmFastModelComponent(Dir(name).File(name + '.sgproj'), + Dir(name).File(name + '.lisa'), + protocol_dir.File( + 'ExportedClockRateControlProtocol.lisa') + ).prepare_env(env) + SimObject('FastModelCortexA76.py') Source('cortex_a76.cc') Source('evs.cc') diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc index 263c100ca..ed5f555ea 100644 --- a/src/arch/arm/fastmodel/CortexA76/evs.cc +++ b/src/arch/arm/fastmodel/CortexA76/evs.cc @@ -150,6 +150,9 @@ ScxEvsCortexA76::gem5_getPort(const std::string &if_name, int idx) } template class ScxEvsCortexA76; +template class ScxEvsCortexA76; +template class ScxEvsCortexA76; +template class ScxEvsCortexA76; } // namespace FastModel @@ -158,3 +161,21 @@ FastModelScxEvsCortexA76x1Params::create() { return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this); } + +FastModel::ScxEvsCortexA76x2 * +FastModelScxEvsCortexA76x2Params::create() +{ + return new FastModel::ScxEvsCortexA76x2(name.c_str(), *this); +} + +FastModel::ScxEvsCortexA76x3 * +FastModelScxEvsCortexA76x3Params::create() +{ + return new FastModel::ScxEvsCortexA76x3(name.c_str(), *this); +} + +FastModel::ScxEvsCortexA76x4 * +FastModelScxEvsCortexA76x4Params::create() +{ + return new FastModel::ScxEvsCortexA76x4(name.c_str(), *this); +} diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh index a9783a3b1..b33ba2854 100644 --- a/src/arch/arm/fastmodel/CortexA76/evs.hh +++ b/src/arch/arm/fastmodel/CortexA76/evs.hh @@ -37,7 +37,13 @@ #include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh" #include "mem/port_proxy.hh" #include "params/FastModelScxEvsCortexA76x1.hh" +#include "params/FastModelScxEvsCortexA76x2.hh" +#include "params/FastModelScxEvsCortexA76x3.hh" +#include "params/FastModelScxEvsCortexA76x4.hh" #include "scx_evs_CortexA76x1.h" +#include "scx_evs_CortexA76x2.h" +#include "scx_evs_CortexA76x3.h" +#include "scx_evs_CortexA76x4.h" #include "systemc/ext/core/sc_event.hh" #include "systemc/ext/core/sc_module.hh" #include "systemc/tlm_port_wrapper.hh" @@ -112,6 +118,33 @@ struct ScxEvsCortexA76x1Types using ScxEvsCortexA76x1 = ScxEvsCortexA76; extern template class ScxEvsCortexA76; +struct ScxEvsCortexA76x2Types +{ + using Base = scx_evs_CortexA76x2; + using Params = FastModelScxEvsCortexA76x2Params; + static const int CoreCount = 2; +}; +using ScxEvsCortexA76x2 = ScxEvsCortexA76; +extern template class ScxEvsCortexA76; + +struct ScxEvsCortexA76x3Types +{ + using Base = scx_evs_CortexA76x3; + using Params = FastModelScxEvsCortexA76x3Params; + static const int CoreCount = 3; +}; +using ScxEvsCortexA76x3 = ScxEvsCortexA76; +extern template class ScxEvsCortexA76; + +struct ScxEvsCortexA76x4Types +{ + using Base = scx_evs_CortexA76x4; + using Params = FastModelScxEvsCortexA76x4Params; + static const int CoreCount = 4; +}; +using ScxEvsCortexA76x4 = ScxEvsCortexA76; +extern template class ScxEvsCortexA76; + } // namespace FastModel #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__ diff --git a/src/arch/arm/fastmodel/CortexA76/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1.lisa deleted file mode 100644 index 942b178a6..000000000 --- a/src/arch/arm/fastmodel/CortexA76/x1.lisa +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2019 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -component CortexA76x1 -{ - - composition - { - core : ARMCortexA76x1CT(); - - // Clocks. - clock1Hz : MasterClock(); - clockDiv : ClockDivider(); - clockDivPeriph : ClockDivider(mul=0x01800000); - } - - connection - { - // The main interface with memory. - core.pvbus_m0 => self.amba; - - // Connection to the GIC. - self.redistributor => core.gicv3_redistributor_s; - - // Core interrupt signals. - core.CNTHPIRQ => self.cnthpirq; - core.CNTHVIRQ => self.cnthvirq; - core.CNTPNSIRQ => self.cntpnsirq; - core.CNTPSIRQ => self.cntpsirq; - core.CNTVIRQ => self.cntvirq; - core.commirq => self.commirq; - core.ctidbgirq => self.ctidbgirq; - core.pmuirq => self.pmuirq; - core.vcpumntirq => self.vcpumntirq; - - // Clocks. - clock1Hz.clk_out => clockDiv.clk_in; - clock1Hz.clk_out => clockDivPeriph.clk_in; - clockDiv.clk_out => core.core_clk_in; - clockDivPeriph.clk_out => core.clk_in; - } - - properties - { - component_type = "System"; - } - - master port amba; - slave port clock_rate_s - { - behavior set_mul_div(uint64_t mul, uint64_t div) - { - clockDiv.rate.set64(mul, div); - } - } - slave port redistributor[1]; - - // External ports for CPU-to-GIC signals - master port cnthpirq[1]; - master port cnthvirq[1]; - master port cntpsirq[1]; - master port cntvirq[1]; - master port commirq[1]; - master port ctidbgirq[1]; - master port pmuirq[1]; - master port vcpumntirq[1]; - master port cntpnsirq[1]; -} diff --git a/src/arch/arm/fastmodel/CortexA76/x1.sgproj b/src/arch/arm/fastmodel/CortexA76/x1.sgproj deleted file mode 100644 index 07f821f1c..000000000 --- a/src/arch/arm/fastmodel/CortexA76/x1.sgproj +++ /dev/null @@ -1,29 +0,0 @@ -sgproject "x1.sgproj" -{ -TOP_LEVEL_COMPONENT = "CortexA76x1"; -ACTIVE_CONFIG_LINUX = "gcc"; -ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; -config "gcc" -{ - ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; - ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; - BUILD_DIR = "./gcc"; - COMPILER = "gcc-6.4"; - CONFIG_DESCRIPTION = ""; - CONFIG_NAME = "gcc"; - PLATFORM = "Linux64"; - PREPROCESSOR_DEFINES = "NDEBUG"; - SIMGEN_COMMAND_LINE = "--num-comps-file 50"; - TARGET_MAXVIEW = "0"; - TARGET_SYSTEMC = "1"; - TARGET_SYSTEMC_AUTO = "1"; - - INCLUDE_DIRS="../../../../"; -} -files -{ - path = "x1.lisa"; - path = "${PVLIB_HOME}/etc/sglib.sgrepo"; - path = "../protocol/ExportedClockRateControlProtocol.lisa"; -} -} diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa new file mode 100644 index 000000000..942b178a6 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa @@ -0,0 +1,94 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +component CortexA76x1 +{ + + composition + { + core : ARMCortexA76x1CT(); + + // Clocks. + clock1Hz : MasterClock(); + clockDiv : ClockDivider(); + clockDivPeriph : ClockDivider(mul=0x01800000); + } + + connection + { + // The main interface with memory. + core.pvbus_m0 => self.amba; + + // Connection to the GIC. + self.redistributor => core.gicv3_redistributor_s; + + // Core interrupt signals. + core.CNTHPIRQ => self.cnthpirq; + core.CNTHVIRQ => self.cnthvirq; + core.CNTPNSIRQ => self.cntpnsirq; + core.CNTPSIRQ => self.cntpsirq; + core.CNTVIRQ => self.cntvirq; + core.commirq => self.commirq; + core.ctidbgirq => self.ctidbgirq; + core.pmuirq => self.pmuirq; + core.vcpumntirq => self.vcpumntirq; + + // Clocks. + clock1Hz.clk_out => clockDiv.clk_in; + clock1Hz.clk_out => clockDivPeriph.clk_in; + clockDiv.clk_out => core.core_clk_in; + clockDivPeriph.clk_out => core.clk_in; + } + + properties + { + component_type = "System"; + } + + master port amba; + slave port clock_rate_s + { + behavior set_mul_div(uint64_t mul, uint64_t div) + { + clockDiv.rate.set64(mul, div); + } + } + slave port redistributor[1]; + + // External ports for CPU-to-GIC signals + master port cnthpirq[1]; + master port cnthvirq[1]; + master port cntpsirq[1]; + master port cntvirq[1]; + master port commirq[1]; + master port ctidbgirq[1]; + master port pmuirq[1]; + master port vcpumntirq[1]; + master port cntpnsirq[1]; +} diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj new file mode 100644 index 000000000..214653f65 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.sgproj @@ -0,0 +1,29 @@ +sgproject "x1.sgproj" +{ +TOP_LEVEL_COMPONENT = "CortexA76x1"; +ACTIVE_CONFIG_LINUX = "gcc"; +ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; +config "gcc" +{ + ADDITIONAL_COMPILER_SETTINGS = "-O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; + ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; + BUILD_DIR = "./gcc"; + COMPILER = "gcc-6.4"; + CONFIG_DESCRIPTION = ""; + CONFIG_NAME = "gcc"; + PLATFORM = "Linux64"; + PREPROCESSOR_DEFINES = "NDEBUG"; + SIMGEN_COMMAND_LINE = "--num-comps-file 50"; + TARGET_MAXVIEW = "0"; + TARGET_SYSTEMC = "1"; + TARGET_SYSTEMC_AUTO = "1"; + + INCLUDE_DIRS="../../../../../"; +} +files +{ + path = "x1.lisa"; + path = "${PVLIB_HOME}/etc/sglib.sgrepo"; + path = "../../protocol/ExportedClockRateControlProtocol.lisa"; +} +} diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa new file mode 100644 index 000000000..091ad1738 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa @@ -0,0 +1,94 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +component CortexA76x2 +{ + + composition + { + core : ARMCortexA76x2CT(); + + // Clocks. + clock1Hz : MasterClock(); + clockDiv : ClockDivider(); + clockDivPeriph : ClockDivider(mul=0x01800000); + } + + connection + { + // The main interface with memory. + core.pvbus_m0 => self.amba; + + // Connection to the GIC. + self.redistributor => core.gicv3_redistributor_s; + + // Core interrupt signals. + core.CNTHPIRQ => self.cnthpirq; + core.CNTHVIRQ => self.cnthvirq; + core.CNTPNSIRQ => self.cntpnsirq; + core.CNTPSIRQ => self.cntpsirq; + core.CNTVIRQ => self.cntvirq; + core.commirq => self.commirq; + core.ctidbgirq => self.ctidbgirq; + core.pmuirq => self.pmuirq; + core.vcpumntirq => self.vcpumntirq; + + // Clocks. + clock1Hz.clk_out => clockDiv.clk_in; + clock1Hz.clk_out => clockDivPeriph.clk_in; + clockDiv.clk_out => core.core_clk_in; + clockDivPeriph.clk_out => core.clk_in; + } + + properties + { + component_type = "System"; + } + + master port amba; + slave port clock_rate_s + { + behavior set_mul_div(uint64_t mul, uint64_t div) + { + clockDiv.rate.set64(mul, div); + } + } + slave port redistributor[2]; + + // External ports for CPU-to-GIC signals + master port cnthpirq[2]; + master port cnthvirq[2]; + master port cntpsirq[2]; + master port cntvirq[2]; + master port commirq[2]; + master port ctidbgirq[2]; + master port pmuirq[2]; + master port vcpumntirq[2]; + master port cntpnsirq[2]; +} diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj new file mode 100644 index 000000000..92eeb4dd3 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.sgproj @@ -0,0 +1,29 @@ +sgproject "x2.sgproj" +{ +TOP_LEVEL_COMPONENT = "CortexA76x2"; +ACTIVE_CONFIG_LINUX = "gcc"; +ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; +config "gcc" +{ + ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; + ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; + BUILD_DIR = "./gcc"; + COMPILER = "gcc-6.4"; + CONFIG_DESCRIPTION = ""; + CONFIG_NAME = "gcc"; + PLATFORM = "Linux64"; + PREPROCESSOR_DEFINES = "NDEBUG"; + SIMGEN_COMMAND_LINE = "--num-comps-file 50"; + TARGET_MAXVIEW = "0"; + TARGET_SYSTEMC = "1"; + TARGET_SYSTEMC_AUTO = "1"; + + INCLUDE_DIRS="../../../../../"; +} +files +{ + path = "x2.lisa"; + path = "${PVLIB_HOME}/etc/sglib.sgrepo"; + path = "../../protocol/ExportedClockRateControlProtocol.lisa"; +} +} diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa new file mode 100644 index 000000000..a78678636 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa @@ -0,0 +1,94 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +component CortexA76x3 +{ + + composition + { + core : ARMCortexA76x3CT(); + + // Clocks. + clock1Hz : MasterClock(); + clockDiv : ClockDivider(); + clockDivPeriph : ClockDivider(mul=0x01800000); + } + + connection + { + // The main interface with memory. + core.pvbus_m0 => self.amba; + + // Connection to the GIC. + self.redistributor => core.gicv3_redistributor_s; + + // Core interrupt signals. + core.CNTHPIRQ => self.cnthpirq; + core.CNTHVIRQ => self.cnthvirq; + core.CNTPNSIRQ => self.cntpnsirq; + core.CNTPSIRQ => self.cntpsirq; + core.CNTVIRQ => self.cntvirq; + core.commirq => self.commirq; + core.ctidbgirq => self.ctidbgirq; + core.pmuirq => self.pmuirq; + core.vcpumntirq => self.vcpumntirq; + + // Clocks. + clock1Hz.clk_out => clockDiv.clk_in; + clock1Hz.clk_out => clockDivPeriph.clk_in; + clockDiv.clk_out => core.core_clk_in; + clockDivPeriph.clk_out => core.clk_in; + } + + properties + { + component_type = "System"; + } + + master port amba; + slave port clock_rate_s + { + behavior set_mul_div(uint64_t mul, uint64_t div) + { + clockDiv.rate.set64(mul, div); + } + } + slave port redistributor[3]; + + // External ports for CPU-to-GIC signals + master port cnthpirq[3]; + master port cnthvirq[3]; + master port cntpsirq[3]; + master port cntvirq[3]; + master port commirq[3]; + master port ctidbgirq[3]; + master port pmuirq[3]; + master port vcpumntirq[3]; + master port cntpnsirq[3]; +} diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj new file mode 100644 index 000000000..e661c4f49 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.sgproj @@ -0,0 +1,29 @@ +sgproject "x3.sgproj" +{ +TOP_LEVEL_COMPONENT = "CortexA76x3"; +ACTIVE_CONFIG_LINUX = "gcc"; +ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; +config "gcc" +{ + ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; + ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; + BUILD_DIR = "./gcc"; + COMPILER = "gcc-6.4"; + CONFIG_DESCRIPTION = ""; + CONFIG_NAME = "gcc"; + PLATFORM = "Linux64"; + PREPROCESSOR_DEFINES = "NDEBUG"; + SIMGEN_COMMAND_LINE = "--num-comps-file 50"; + TARGET_MAXVIEW = "0"; + TARGET_SYSTEMC = "1"; + TARGET_SYSTEMC_AUTO = "1"; + + INCLUDE_DIRS="../../../../../"; +} +files +{ + path = "x3.lisa"; + path = "${PVLIB_HOME}/etc/sglib.sgrepo"; + path = "../../protocol/ExportedClockRateControlProtocol.lisa"; +} +} diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa new file mode 100644 index 000000000..6926f491a --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa @@ -0,0 +1,94 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +component CortexA76x4 +{ + + composition + { + core : ARMCortexA76x4CT(); + + // Clocks. + clock1Hz : MasterClock(); + clockDiv : ClockDivider(); + clockDivPeriph : ClockDivider(mul=0x01800000); + } + + connection + { + // The main interface with memory. + core.pvbus_m0 => self.amba; + + // Connection to the GIC. + self.redistributor => core.gicv3_redistributor_s; + + // Core interrupt signals. + core.CNTHPIRQ => self.cnthpirq; + core.CNTHVIRQ => self.cnthvirq; + core.CNTPNSIRQ => self.cntpnsirq; + core.CNTPSIRQ => self.cntpsirq; + core.CNTVIRQ => self.cntvirq; + core.commirq => self.commirq; + core.ctidbgirq => self.ctidbgirq; + core.pmuirq => self.pmuirq; + core.vcpumntirq => self.vcpumntirq; + + // Clocks. + clock1Hz.clk_out => clockDiv.clk_in; + clock1Hz.clk_out => clockDivPeriph.clk_in; + clockDiv.clk_out => core.core_clk_in; + clockDivPeriph.clk_out => core.clk_in; + } + + properties + { + component_type = "System"; + } + + master port amba; + slave port clock_rate_s + { + behavior set_mul_div(uint64_t mul, uint64_t div) + { + clockDiv.rate.set64(mul, div); + } + } + slave port redistributor[4]; + + // External ports for CPU-to-GIC signals + master port cnthpirq[4]; + master port cnthvirq[4]; + master port cntpsirq[4]; + master port cntvirq[4]; + master port commirq[4]; + master port ctidbgirq[4]; + master port pmuirq[4]; + master port vcpumntirq[4]; + master port cntpnsirq[4]; +} diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj new file mode 100644 index 000000000..5b7f31542 --- /dev/null +++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.sgproj @@ -0,0 +1,29 @@ +sgproject "x4.sgproj" +{ +TOP_LEVEL_COMPONENT = "CortexA76x4"; +ACTIVE_CONFIG_LINUX = "gcc"; +ACTIVE_CONFIG_WINDOWS = "Win64-Release-VC2015"; +config "gcc" +{ + ADDITIONAL_COMPILER_SETTINGS = "-march=core2 -O3 -Wall -std=c++11 -Wno-deprecated -Wno-unused-function"; + ADDITIONAL_LINKER_SETTINGS = "-Wl,--no-undefined"; + BUILD_DIR = "./gcc"; + COMPILER = "gcc-6.4"; + CONFIG_DESCRIPTION = ""; + CONFIG_NAME = "gcc"; + PLATFORM = "Linux64"; + PREPROCESSOR_DEFINES = "NDEBUG"; + SIMGEN_COMMAND_LINE = "--num-comps-file 50"; + TARGET_MAXVIEW = "0"; + TARGET_SYSTEMC = "1"; + TARGET_SYSTEMC_AUTO = "1"; + + INCLUDE_DIRS="../../../../../"; +} +files +{ + path = "x4.lisa"; + path = "${PVLIB_HOME}/etc/sglib.sgrepo"; + path = "../../protocol/ExportedClockRateControlProtocol.lisa"; +} +}