From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 8 May 2020 20:11:41 +0000 (-0400)
Subject: Add comments about the purpose of each alu stage
X-Git-Tag: div_pipeline~1333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40269cae92d87ab5ffc864e3e45ff3651c565264;p=soc.git

Add comments about the purpose of each alu stage
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 6d5e1e46..77da32f5 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -1,3 +1,7 @@
+# This stage is intended to adjust the input data before sending it to
+# the acutal ALU. Things like handling inverting the input, carry_in
+# generation for subtraction, and handling of immediates should happen
+# here
 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 615a7845..e801c966 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -1,3 +1,8 @@
+# This stage is intended to do most of the work of executing the ALU
+# instructions. This would be like the additions, logical operations,
+# and shifting, as well as carry and overflow generation. This module
+# however should not gate the carry or overflow, that's up to the
+# output stage
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData, ALUOutputData
diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index cb63b0e4..1a8a82b6 100644
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -1,3 +1,6 @@
+# This stage is intended to handle the gating of carry and overflow
+# out, summary overflow generation, and updating the condition
+# register
 from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData, ALUOutputData