From: R Veera Kumar <vklr@vkten.in>
Date: Thu, 25 Nov 2021 09:45:18 +0000 (+0530)
Subject: Correct add-equal operator in case_rand_imm
X-Git-Tag: sv_maxu_works-initial~699
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=402adaee4f2c204ad3d725ef219385690ed3cae8;p=openpower-isa.git

Correct add-equal operator in case_rand_imm
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index b78f411f..5cb07aed 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -268,7 +268,7 @@ class ALUTestCase(TestAccumulatorBase):
                 result = ~initial_regs[1] + imm + 1
                 value = (~initial_regs[1]+2**64) + (imm) + 1
                 if imm < 0:
-                    value =+ 2**64
+                    value += 2**64
                 carry_out = value & (1<<64) != 0
                 if imm >= 0:
                     carry_out32 = (((~initial_regs[1]+2**64) & 0xffff_ffff) + \