From: Tim Newsome <tim@sifive.com>
Date: Wed, 27 Jul 2016 23:05:09 +0000 (-0700)
Subject: Rename m2gl_m2s to freedom-e300. (#19)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=402d4538783ee7a048809dfa0ce923eca9d3f868;p=riscv-tests.git

Rename m2gl_m2s to freedom-e300. (#19)

It's possible to flash the Freedom E300 onto different FPGA boards, and
then debug them in the exact same way.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 1d5c60e..a3f8153 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -505,8 +505,8 @@ class Spike32Target(SpikeTarget):
     def server(self):
         return testlib.Spike(parsed.cmd, halted=True, xlen=32)
 
-class MicroSemiTarget(Target):
-    name = "m2gl_m2s"
+class FreedomE300Target(Target):
+    name = "freedom-e300"
     xlen = 32
     ram = 0x80000000
     ram_size = 16 * 1024
@@ -519,7 +519,7 @@ class MicroSemiTarget(Target):
 targets = [
         Spike32Target,
         Spike64Target,
-        MicroSemiTarget
+        FreedomE300Target
         ]
 
 def main():
diff --git a/debug/targets/freedom-e300/link.lds b/debug/targets/freedom-e300/link.lds
new file mode 100755
index 0000000..1dbb99c
--- /dev/null
+++ b/debug/targets/freedom-e300/link.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    _gp = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
new file mode 100644
index 0000000..3884a3e
--- /dev/null
+++ b/debug/targets/freedom-e300/openocd.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+#reset_config trst_and_srst separate
+# Stupid long so I can see the LEDs
+#adapter_nsrst_delay 2000
+#jtag_ntrst_delay 1000
+#
+init
+#reset
+
+halt
diff --git a/debug/targets/m2gl_m2s/link.lds b/debug/targets/m2gl_m2s/link.lds
deleted file mode 100755
index 1dbb99c..0000000
--- a/debug/targets/m2gl_m2s/link.lds
+++ /dev/null
@@ -1,34 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
-  . = 0x80000000;
-  .text : 
-  {
-    *(.text.entry)
-    *(.text)
-  }
-
-  /* data segment */
-  .data : { *(.data) }
-
-  .sdata : {
-    _gp = . + 0x800;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
-    *(.srodata*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-
-  /* bss segment */
-  .sbss : {
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  }
-  .bss : { *(.bss) }
-
-  __malloc_start = .;
-  . = . + 512;
-
-  /* End of uninitalized data segement */
-  _end = .;
-}
diff --git a/debug/targets/m2gl_m2s/openocd.cfg b/debug/targets/m2gl_m2s/openocd.cfg
deleted file mode 100644
index 3884a3e..0000000
--- a/debug/targets/m2gl_m2s/openocd.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-adapter_khz     10000
-
-source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-#reset_config trst_and_srst separate
-# Stupid long so I can see the LEDs
-#adapter_nsrst_delay 2000
-#jtag_ntrst_delay 1000
-#
-init
-#reset
-
-halt