From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 20:35:25 +0000 (-0800)
Subject: Revert "Fold loop"
X-Git-Tag: working-ls180~881^2^2~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=403214f44d8f447ce4e367e2d7e135bfaabcb88d;p=yosys.git

Revert "Fold loop"

This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f17a4c775..8b809b2e2 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -184,7 +184,6 @@ struct XAigerWriter
 					if (bit != wirebit)
 						alias_map[bit] = wirebit;
 					input_bits.insert(wirebit);
-					undriven_bits.erase(bit);
 				}
 
 				if (wire->port_output || keep) {
@@ -192,8 +191,6 @@ struct XAigerWriter
 						if (bit != wirebit)
 							alias_map[wirebit] = bit;
 						output_bits.insert(wirebit);
-						if (!wire->port_input)
-							unused_bits.erase(bit);
 					}
 					else
 						log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@@ -201,6 +198,12 @@ struct XAigerWriter
 			}
 		}
 
+		for (auto bit : input_bits)
+			undriven_bits.erase(sigmap(bit));
+		for (auto bit : output_bits)
+			if (!bit.wire->port_input)
+				unused_bits.erase(bit);
+
 		// TODO: Speed up toposort -- ultimately we care about
 		//       box ordering, but not individual AIG cells
 		dict<SigBit, pool<IdString>> bit_drivers, bit_users;