From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Sep 2022 07:12:41 +0000 (+0100)
Subject: add svstate param to constructor of StepLoop, ISACaller
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4032bdefea429832d2d50bb1eb181f560750f78b;p=openpower-isa.git

add svstate param to constructor of StepLoop, ISACaller
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3fe5e284..cdf7f416 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -527,8 +527,8 @@ class StepLoop:
     """deals with svstate looping.
     """
 
-    def __init__(self):
-        pass
+    def __init__(self, svstate):
+        self.svstate = svstate
 
     def advance_svstate_steps(self, end_src=False, end_dst=False):
         """ advance sub/steps. note that Pack/Unpack *INVERTS* the order.
@@ -742,7 +742,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if isinstance(initial_svstate, int):
             initial_svstate = SVP64State(initial_svstate)
         # SVSTATE, MSR and PC
-        self.svstate = initial_svstate
+        StepLoop.__init__(self, initial_svstate)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
         self.pc = PC()
         # GPR FPR SPR registers