From: Clifford Wolf Date: Mon, 21 Oct 2019 10:39:28 +0000 (+0200) Subject: Fix handling of "restrict" in Verific front-end X-Git-Tag: working-ls180~982 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7;p=yosys.git Fix handling of "restrict" in Verific front-end Signed-off-by: Clifford Wolf --- diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c5eef4b55..9f9eeb764 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1256,7 +1256,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT) sva_asserts.insert(inst); - if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME) + if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_RESTRICT) sva_assumes.insert(inst); if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER)