From: DJ Delorie <dj@redhat.com>
Date: Wed, 8 Apr 2009 20:39:35 +0000 (+0000)
Subject: [cgen]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40493983ad5cdac9625b3f2a1f92e41e094fde4c;p=binutils-gdb.git

[cgen]
	* cpu/mep-c5.cpu: New.
	* cpu/mep-core.cpu: Add C5 support.
	* cpu/mep.opc: Likewise.
[opcodes]
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
[sid]
	* component/cache/cache.cxx (cache_component::cache_component):
	Add write_hint_pin().  Attach it to write-hint.
	(cache_component::write_hint): New.
	* component/cache/cache.h (write_hint_pin): New.
	(write_hint): New.

	* component/cgen-cpu/mep/Makefile.am: Regenerate.
	* component/cgen-cpu/mep/Makefile.in: Regenerate.
	* component/cgen-cpu/mep/mep-core1-decode.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-core1-decode.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-defs.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-model.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-core1-model.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-sem.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-decode.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-decode.h: Regenerate.
	* component/cgen-cpu/mep/mep-defs.h: Regenerate.
	* component/cgen-cpu/mep/mep-desc.h: Regenerate.
	* component/cgen-cpu/mep/mep-model.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-model.h: Regenerate.
	* component/cgen-cpu/mep/mep-sem.cxx: Regenerate.
	* component/cgen-cpu/mep/mep.cxx (mep_cpu): Connect
	write-hint pin.
	(do_cache): Add C5 support.
	(do_cache_prefetch): Likewise.
	(do_casb3, do_cash3, do_casw3): New.
	* component/cgen-cpu/mep/mep.h: Add C5 support and write-hint pin.
	(do_casb3, do_cash3, do_casw3): New.

	* component/families/mep/Makefile.in: Regenerate.
	* component/families/mep/dsu.in: Add C5 support.
	* main/dynamic/mainDynamic.cxx: Add C5 support.
	* main/dynamic/mepCfg.cxx: Connect write-hint pin.
	* main/dynamic/mepCfg.h: Add C5 support.
---

diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 43ca942fc18..41a1f92fd09 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -51,6 +51,8 @@ static const char * parse_insn_normal
 
 /* -- asm.c */
 
+#include "elf/mep.h"
+
 #define CGEN_VALIDATE_INSN_SUPPORTED
 
        const char * parse_csrn       (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
@@ -126,9 +128,6 @@ parse_mep_align (CGEN_CPU_DESC cd, const char ** strp,
     case MEP_OPERAND_PCREL12A2:
     case MEP_OPERAND_PCREL17A2:
     case MEP_OPERAND_PCREL24A2:
-    case MEP_OPERAND_CDISP8A2:
-    case MEP_OPERAND_CDISP8A4:
-    case MEP_OPERAND_CDISP8A8:
       err = cgen_parse_signed_integer   (cd, strp, type, field);
       break;
     case MEP_OPERAND_PCABS24A2:
@@ -155,16 +154,13 @@ parse_mep_align (CGEN_CPU_DESC cd, const char ** strp,
     case MEP_OPERAND_PCREL24A2:
     case MEP_OPERAND_PCABS24A2:
     case MEP_OPERAND_UDISP7A2:
-    case MEP_OPERAND_CDISP8A2:
       lsbs = *field & 1;
       break;
     case MEP_OPERAND_UDISP7A4:
     case MEP_OPERAND_UIMM7A4:
     case MEP_OPERAND_ADDR24A4:
-    case MEP_OPERAND_CDISP8A4:
       lsbs = *field & 3;
       break;
-    case MEP_OPERAND_CDISP8A8:
       lsbs = *field & 7;
       break;
     default:
@@ -441,6 +437,66 @@ parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp,
   return parse_mep_alignu (cd, strp, opindex, valuep);
 }
 
+static ATTRIBUTE_UNUSED const char *
+parse_cdisp10 (CGEN_CPU_DESC cd,
+	       const char **strp,
+	       int opindex,
+	       long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+  int wide = 0;
+  int alignment;
+
+  switch (opindex)
+    {
+    case MEP_OPERAND_CDISP10A4:
+      alignment = 2;
+      break;
+    case MEP_OPERAND_CDISP10A2:
+      alignment = 1;
+      break;
+    case MEP_OPERAND_CDISP10:
+    default:
+      alignment = 0;
+      break;
+    }
+
+  if (MEP_CPU == EF_MEP_CPU_C5)
+    wide = 1;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (wide)
+    {
+      if (value < -512 || value > 511)
+	return _("Immediate is out of range -512 to 511");
+    }
+  else
+    {
+      if (value < -128 || value > 127)
+	return _("Immediate is out of range -128 to 127");
+    }
+
+  if (value & ((1<<alignment)-1))
+    return _("Value is not aligned enough");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return (wide ? _("Immediate is out of range -512 to 511")
+	    : _("Immediate is out of range -128 to 127"));
+
+  *valuep = value;
+  return 0;
+}
+
 /* BEGIN LIGHTWEIGHT MACRO PROCESSOR.  */
 
 #define MAXARGS 9
@@ -727,6 +783,12 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_ADDR24A4 :
       errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_ADDR24A4, (unsigned long *) (& fields->f_24u8a4n));
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RMUIMM20, (unsigned long *) (& fields->f_c5_rmuimm20));
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RNMUIMM24, (unsigned long *) (& fields->f_c5_rnmuimm24));
+      break;
     case MEP_OPERAND_CALLNUM :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CALLNUM, (unsigned long *) (& fields->f_callnum));
       break;
@@ -736,17 +798,20 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_CCRN :
       errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ccrn);
       break;
-    case MEP_OPERAND_CDISP8 :
-      errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP8, (long *) (& fields->f_8s24));
+    case MEP_OPERAND_CDISP10 :
+      errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10, (long *) (& fields->f_cdisp10));
+      break;
+    case MEP_OPERAND_CDISP10A2 :
+      errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A2, (long *) (& fields->f_cdisp10));
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A2, (long *) (& fields->f_8s24a2));
+    case MEP_OPERAND_CDISP10A4 :
+      errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A4, (long *) (& fields->f_cdisp10));
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A4, (long *) (& fields->f_8s24a4));
+    case MEP_OPERAND_CDISP10A8 :
+      errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A8, (long *) (& fields->f_cdisp10));
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A8, (long *) (& fields->f_8s24a8));
+    case MEP_OPERAND_CDISP12 :
+      errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP12, (long *) (& fields->f_12s20));
       break;
     case MEP_OPERAND_CIMM4 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM4, (unsigned long *) (& fields->f_rn));
@@ -847,6 +912,9 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_RL :
       errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl);
       break;
+    case MEP_OPERAND_RL5 :
+      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl5);
+      break;
     case MEP_OPERAND_RM :
       errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm);
       break;
diff --git a/opcodes/mep-desc.c b/opcodes/mep-desc.c
index 88f958c3ade..a210bdabc35 100644
--- a/opcodes/mep-desc.c
+++ b/opcodes/mep-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
   { "base", MACH_BASE },
   { "mep", MACH_MEP },
   { "h1", MACH_H1 },
+  { "c5", MACH_C5 },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -193,6 +194,7 @@ static const CGEN_ISA mep_cgen_isa_table[] = {
 static const CGEN_MACH mep_cgen_mach_table[] = {
   { "mep", "mep", MACH_MEP, 16 },
   { "h1", "h1", MACH_H1, 16 },
+  { "c5", "c5", MACH_C5, 16 },
   { 0, 0, 0, 0 }
 };
 
@@ -473,6 +475,8 @@ const CGEN_IFLD mep_cgen_ifld_table[] =
   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
@@ -536,10 +540,7 @@ const CGEN_IFLD mep_cgen_ifld_table[] =
   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
@@ -553,6 +554,17 @@ const CGEN_IFLD mep_cgen_ifld_table[] =
   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
@@ -571,6 +583,8 @@ const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
 
 
 /* multi ifield definitions */
@@ -631,6 +645,18 @@ const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
     { 0, { (const PTR) 0 } }
 };
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
+    { 0, { (const PTR) 0 } }
+};
 
 /* The operand table.  */
 
@@ -939,26 +965,42 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
-/* cdisp8: copro addend (8 bits) */
-  { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8,
-    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } }, 
+/* cdisp10: comment */
+  { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* cdisp10a2: comment */
+  { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* cdisp10a4: comment */
+  { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* cdisp10a8: comment */
+  { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
-/* cdisp8a2: comment */
-  { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7,
-    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } }, 
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
-/* cdisp8a4: comment */
-  { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6,
-    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } }, 
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
-/* cdisp8a8: comment */
-  { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5,
-    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } }, 
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } }  },
 /* zero: Zero operand */
   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* rl5: register Rl c5 */
+  { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* cdisp12: copro addend (12 bits) */
+  { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* c5rmuimm20: 20-bit immediate in rm and imm16 */
+  { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
+    { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
+  { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
+    { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 /* cp_flag: branch condition register */
   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
     { 0, { (const PTR) 0 } }, 
@@ -987,6 +1029,111 @@ static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
+/* stcb $rn,($rma) */
+  {
+    MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* ldcb $rn,($rma) */
+  {
+    MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* pref $cimm4,($rma) */
+  {
+    MEP_INSN_PREF, "pref", "pref", 16,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* pref $cimm4,$sdisp16($rma) */
+  {
+    MEP_INSN_PREFD, "prefd", "pref", 32,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* casb3 $rl5,$rn,($rm) */
+  {
+    MEP_INSN_CASB3, "casb3", "casb3", 32,
+    { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* cash3 $rl5,$rn,($rm) */
+  {
+    MEP_INSN_CASH3, "cash3", "cash3", 32,
+    { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* casw3 $rl5,$rn,($rm) */
+  {
+    MEP_INSN_CASW3, "casw3", "casw3", 32,
+    { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* sbcp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_SBCP, "sbcp", "sbcp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lbcp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_LBCP, "lbcp", "lbcp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lbucp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* shcp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_SHCP, "shcp", "shcp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lhcp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_LHCP, "lhcp", "lhcp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lhucp $crn,$cdisp12($rma) */
+  {
+    MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lbucpa $crn,($rma+),$cdisp10 */
+  {
+    MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lhucpa $crn,($rma+),$cdisp10a2 */
+  {
+    MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lbucpm0 $crn,($rma+),$cdisp10 */
+  {
+    MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lhucpm0 $crn,($rma+),$cdisp10a2 */
+  {
+    MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lbucpm1 $crn,($rma+),$cdisp10 */
+  {
+    MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* lhucpm1 $crn,($rma+),$cdisp10a2 */
+  {
+    MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* uci $rn,$rm,$uimm16 */
+  {
+    MEP_INSN_UCI, "uci", "uci", 32,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* dsp $rn,$rm,$uimm16 */
+  {
+    MEP_INSN_DSP, "dsp", "dsp", 32,
+    { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
 /* sb $rnc,($rma) */
   {
     MEP_INSN_SB, "sb", "sb", 16,
@@ -1727,122 +1874,122 @@ static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* sbcpa $crn,($rma+),$cdisp8 */
+/* sbcpa $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lbcpa $crn,($rma+),$cdisp8 */
+/* lbcpa $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* shcpa $crn,($rma+),$cdisp8a2 */
+/* shcpa $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lhcpa $crn,($rma+),$cdisp8a2 */
+/* lhcpa $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* swcpa $crn,($rma+),$cdisp8a4 */
+/* swcpa $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lwcpa $crn,($rma+),$cdisp8a4 */
+/* lwcpa $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* smcpa $crn64,($rma+),$cdisp8a8 */
+/* smcpa $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lmcpa $crn64,($rma+),$cdisp8a8 */
+/* lmcpa $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* sbcpm0 $crn,($rma+),$cdisp8 */
+/* sbcpm0 $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lbcpm0 $crn,($rma+),$cdisp8 */
+/* lbcpm0 $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* shcpm0 $crn,($rma+),$cdisp8a2 */
+/* shcpm0 $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lhcpm0 $crn,($rma+),$cdisp8a2 */
+/* lhcpm0 $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* swcpm0 $crn,($rma+),$cdisp8a4 */
+/* swcpm0 $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lwcpm0 $crn,($rma+),$cdisp8a4 */
+/* lwcpm0 $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* smcpm0 $crn64,($rma+),$cdisp8a8 */
+/* smcpm0 $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lmcpm0 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm0 $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* sbcpm1 $crn,($rma+),$cdisp8 */
+/* sbcpm1 $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lbcpm1 $crn,($rma+),$cdisp8 */
+/* lbcpm1 $crn,($rma+),$cdisp10 */
   {
     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* shcpm1 $crn,($rma+),$cdisp8a2 */
+/* shcpm1 $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lhcpm1 $crn,($rma+),$cdisp8a2 */
+/* lhcpm1 $crn,($rma+),$cdisp10a2 */
   {
     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* swcpm1 $crn,($rma+),$cdisp8a4 */
+/* swcpm1 $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lwcpm1 $crn,($rma+),$cdisp8a4 */
+/* lwcpm1 $crn,($rma+),$cdisp10a4 */
   {
     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* smcpm1 $crn64,($rma+),$cdisp8a8 */
+/* smcpm1 $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* lmcpm1 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm1 $crn64,($rma+),$cdisp10a8 */
   {
     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
@@ -1992,36 +2139,11 @@ static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* --reserved-- */
-  {
-    MEP_INSN_RI_24, "ri-24", "--reserved--", 16,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
-  },
-/* --reserved-- */
-  {
-    MEP_INSN_RI_25, "ri-25", "--reserved--", 16,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
-  },
 /* --reserved-- */
   {
     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
   },
-/* --reserved-- */
-  {
-    MEP_INSN_RI_16, "ri-16", "--reserved--", 16,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
-  },
-/* --reserved-- */
-  {
-    MEP_INSN_RI_18, "ri-18", "--reserved--", 16,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
-  },
-/* --reserved-- */
-  {
-    MEP_INSN_RI_19, "ri-19", "--reserved--", 16,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
-  },
 };
 
 #undef OP
diff --git a/opcodes/mep-desc.h b/opcodes/mep-desc.h
index 06640649a13..b4de4d559cc 100644
--- a/opcodes/mep-desc.h
+++ b/opcodes/mep-desc.h
@@ -51,7 +51,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 #define CGEN_INT_INSN_P 1
 
 /* Maximum number of syntax elements in an instruction.  */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 18
 
 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
@@ -75,7 +75,8 @@ typedef enum major {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
+  MACH_BASE, MACH_MEP, MACH_H1, MACH_C5
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -127,27 +128,30 @@ typedef enum cgen_ifld_attr {
 typedef enum ifield_type {
   MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
  , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
- , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
- , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
- , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
- , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
- , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
- , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
- , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
- , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
- , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
- , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
- , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
- , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
- , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
- , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
- , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
- , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
- , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
- , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
- , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
- , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
- , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_MAX
+ , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4
+ , MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO
+ , MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX
+ , MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3
+ , MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7
+ , MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11
+ , MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15
+ , MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19
+ , MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23
+ , MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27
+ , MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31
+ , MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI
+ , MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO
+ , MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2
+ , MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5
+ , MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8
+ , MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29
+ , MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N
+ , MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI
+ , MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI
+ , MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5
+ , MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20
+ , MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20
+ , MEP_F_C5_RNMUIMM24, MEP_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) MEP_F_MAX)
@@ -230,12 +234,13 @@ typedef enum cgen_operand_type {
  , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
  , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
  , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
- , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
- , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
+ , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
+ , MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
+ , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 79
+#define MAX_OPERANDS 83
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index 4eacb9a6607..93f747faf0b 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -500,6 +500,12 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_ADDR24A4 :
       print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
     case MEP_OPERAND_CALLNUM :
       print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
       break;
@@ -509,17 +515,20 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_CCRN :
       print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
       break;
-    case MEP_OPERAND_CDISP8 :
-      print_normal (cd, info, fields->f_8s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+    case MEP_OPERAND_CDISP10 :
+      print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      print_normal (cd, info, fields->f_8s24a2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+    case MEP_OPERAND_CDISP10A2 :
+      print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      print_normal (cd, info, fields->f_8s24a4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+    case MEP_OPERAND_CDISP10A4 :
+      print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      print_normal (cd, info, fields->f_8s24a8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+    case MEP_OPERAND_CDISP10A8 :
+      print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case MEP_OPERAND_CDISP12 :
+      print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
     case MEP_OPERAND_CIMM4 :
       print_normal (cd, info, fields->f_rn, 0, pc, length);
@@ -620,6 +629,9 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_RL :
       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
       break;
+    case MEP_OPERAND_RL5 :
+      print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
+      break;
     case MEP_OPERAND_RM :
       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
       break;
diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c
index ac44ee2535e..947390690b5 100644
--- a/opcodes/mep-ibld.c
+++ b/opcodes/mep-ibld.c
@@ -579,6 +579,34 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
           break;
       }
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      {
+{
+  FLD (f_c5_rm) = ((unsigned int) (FLD (f_c5_rmuimm20)) >> (16));
+  FLD (f_c5_16u16) = ((FLD (f_c5_rmuimm20)) & (65535));
+}
+        errmsg = insert_normal (cd, fields->f_c5_rm, 0, 0, 8, 4, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      {
+{
+  FLD (f_c5_rnm) = ((unsigned int) (FLD (f_c5_rnmuimm24)) >> (16));
+  FLD (f_c5_16u16) = ((FLD (f_c5_rnmuimm24)) & (65535));
+}
+        errmsg = insert_normal (cd, fields->f_c5_rnm, 0, 0, 4, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
     case MEP_OPERAND_CALLNUM :
       {
 {
@@ -618,30 +646,37 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
           break;
       }
       break;
-    case MEP_OPERAND_CDISP8 :
-      errmsg = insert_normal (cd, fields->f_8s24, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, buffer);
+    case MEP_OPERAND_CDISP10 :
+      {
+        long value = fields->f_cdisp10;
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
+      }
       break;
-    case MEP_OPERAND_CDISP8A2 :
+    case MEP_OPERAND_CDISP10A2 :
       {
-        long value = fields->f_8s24a2;
-        value = ((int) (value) >> (1));
-        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, buffer);
+        long value = fields->f_cdisp10;
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
       }
       break;
-    case MEP_OPERAND_CDISP8A4 :
+    case MEP_OPERAND_CDISP10A4 :
       {
-        long value = fields->f_8s24a4;
-        value = ((int) (value) >> (2));
-        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, buffer);
+        long value = fields->f_cdisp10;
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
       }
       break;
-    case MEP_OPERAND_CDISP8A8 :
+    case MEP_OPERAND_CDISP10A8 :
       {
-        long value = fields->f_8s24a8;
-        value = ((int) (value) >> (3));
-        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, buffer);
+        long value = fields->f_cdisp10;
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
       }
       break;
+    case MEP_OPERAND_CDISP12 :
+      errmsg = insert_normal (cd, fields->f_12s20, 0, 0, 20, 12, 32, total_length, buffer);
+      break;
     case MEP_OPERAND_CIMM4 :
       errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer);
       break;
@@ -814,6 +849,9 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_RL :
       errmsg = insert_normal (cd, fields->f_rl, 0, 0, 12, 4, 32, total_length, buffer);
       break;
+    case MEP_OPERAND_RL5 :
+      errmsg = insert_normal (cd, fields->f_rl5, 0, 0, 20, 4, 32, total_length, buffer);
+      break;
     case MEP_OPERAND_RM :
       errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer);
       break;
@@ -994,6 +1032,28 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
   FLD (f_24u8a4n) = ((((FLD (f_24u8a4n_hi)) << (8))) | (((FLD (f_24u8a4n_lo)) << (2))));
       }
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_c5_rm);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16);
+        if (length <= 0) break;
+{
+  FLD (f_c5_rmuimm20) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rm)) << (16))));
+}
+      }
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_c5_rnm);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16);
+        if (length <= 0) break;
+{
+  FLD (f_c5_rnmuimm24) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rnm)) << (16))));
+}
+      }
+      break;
     case MEP_OPERAND_CALLNUM :
       {
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5);
@@ -1019,33 +1079,41 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
   FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo)));
       }
       break;
-    case MEP_OPERAND_CDISP8 :
-      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, pc, & fields->f_8s24);
+    case MEP_OPERAND_CDISP10 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        fields->f_cdisp10 = value;
+      }
       break;
-    case MEP_OPERAND_CDISP8A2 :
+    case MEP_OPERAND_CDISP10A2 :
       {
         long value;
-        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, pc, & value);
-        value = ((value) << (1));
-        fields->f_8s24a2 = value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        fields->f_cdisp10 = value;
       }
       break;
-    case MEP_OPERAND_CDISP8A4 :
+    case MEP_OPERAND_CDISP10A4 :
       {
         long value;
-        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, pc, & value);
-        value = ((value) << (2));
-        fields->f_8s24a4 = value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        fields->f_cdisp10 = value;
       }
       break;
-    case MEP_OPERAND_CDISP8A8 :
+    case MEP_OPERAND_CDISP10A8 :
       {
         long value;
-        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, pc, & value);
-        value = ((value) << (3));
-        fields->f_8s24a8 = value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+        value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+        fields->f_cdisp10 = value;
       }
       break;
+    case MEP_OPERAND_CDISP12 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 12, 32, total_length, pc, & fields->f_12s20);
+      break;
     case MEP_OPERAND_CIMM4 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn);
       break;
@@ -1185,6 +1253,9 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_RL :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_rl);
       break;
+    case MEP_OPERAND_RL5 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_rl5);
+      break;
     case MEP_OPERAND_RM :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm);
       break;
@@ -1352,6 +1423,12 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_ADDR24A4 :
       value = fields->f_24u8a4n;
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      value = fields->f_c5_rmuimm20;
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      value = fields->f_c5_rnmuimm24;
+      break;
     case MEP_OPERAND_CALLNUM :
       value = fields->f_callnum;
       break;
@@ -1361,17 +1438,20 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_CCRN :
       value = fields->f_ccrn;
       break;
-    case MEP_OPERAND_CDISP8 :
-      value = fields->f_8s24;
+    case MEP_OPERAND_CDISP10 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      value = fields->f_8s24a2;
+    case MEP_OPERAND_CDISP10A2 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      value = fields->f_8s24a4;
+    case MEP_OPERAND_CDISP10A4 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      value = fields->f_8s24a8;
+    case MEP_OPERAND_CDISP10A8 :
+      value = fields->f_cdisp10;
+      break;
+    case MEP_OPERAND_CDISP12 :
+      value = fields->f_12s20;
       break;
     case MEP_OPERAND_CIMM4 :
       value = fields->f_rn;
@@ -1472,6 +1552,9 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_RL :
       value = fields->f_rl;
       break;
+    case MEP_OPERAND_RL5 :
+      value = fields->f_rl5;
+      break;
     case MEP_OPERAND_RM :
       value = fields->f_rm;
       break;
@@ -1606,6 +1689,12 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_ADDR24A4 :
       value = fields->f_24u8a4n;
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      value = fields->f_c5_rmuimm20;
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      value = fields->f_c5_rnmuimm24;
+      break;
     case MEP_OPERAND_CALLNUM :
       value = fields->f_callnum;
       break;
@@ -1615,17 +1704,20 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_CCRN :
       value = fields->f_ccrn;
       break;
-    case MEP_OPERAND_CDISP8 :
-      value = fields->f_8s24;
+    case MEP_OPERAND_CDISP10 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      value = fields->f_8s24a2;
+    case MEP_OPERAND_CDISP10A2 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      value = fields->f_8s24a4;
+    case MEP_OPERAND_CDISP10A4 :
+      value = fields->f_cdisp10;
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      value = fields->f_8s24a8;
+    case MEP_OPERAND_CDISP10A8 :
+      value = fields->f_cdisp10;
+      break;
+    case MEP_OPERAND_CDISP12 :
+      value = fields->f_12s20;
       break;
     case MEP_OPERAND_CIMM4 :
       value = fields->f_rn;
@@ -1726,6 +1818,9 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_RL :
       value = fields->f_rl;
       break;
+    case MEP_OPERAND_RL5 :
+      value = fields->f_rl5;
+      break;
     case MEP_OPERAND_RM :
       value = fields->f_rm;
       break;
@@ -1867,6 +1962,12 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_ADDR24A4 :
       fields->f_24u8a4n = value;
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      fields->f_c5_rmuimm20 = value;
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      fields->f_c5_rnmuimm24 = value;
+      break;
     case MEP_OPERAND_CALLNUM :
       fields->f_callnum = value;
       break;
@@ -1876,17 +1977,20 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_CCRN :
       fields->f_ccrn = value;
       break;
-    case MEP_OPERAND_CDISP8 :
-      fields->f_8s24 = value;
+    case MEP_OPERAND_CDISP10 :
+      fields->f_cdisp10 = value;
+      break;
+    case MEP_OPERAND_CDISP10A2 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      fields->f_8s24a2 = value;
+    case MEP_OPERAND_CDISP10A4 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      fields->f_8s24a4 = value;
+    case MEP_OPERAND_CDISP10A8 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      fields->f_8s24a8 = value;
+    case MEP_OPERAND_CDISP12 :
+      fields->f_12s20 = value;
       break;
     case MEP_OPERAND_CIMM4 :
       fields->f_rn = value;
@@ -1970,6 +2074,9 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_RL :
       fields->f_rl = value;
       break;
+    case MEP_OPERAND_RL5 :
+      fields->f_rl5 = value;
+      break;
     case MEP_OPERAND_RM :
       fields->f_rm = value;
       break;
@@ -2095,6 +2202,12 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_ADDR24A4 :
       fields->f_24u8a4n = value;
       break;
+    case MEP_OPERAND_C5RMUIMM20 :
+      fields->f_c5_rmuimm20 = value;
+      break;
+    case MEP_OPERAND_C5RNMUIMM24 :
+      fields->f_c5_rnmuimm24 = value;
+      break;
     case MEP_OPERAND_CALLNUM :
       fields->f_callnum = value;
       break;
@@ -2104,17 +2217,20 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_CCRN :
       fields->f_ccrn = value;
       break;
-    case MEP_OPERAND_CDISP8 :
-      fields->f_8s24 = value;
+    case MEP_OPERAND_CDISP10 :
+      fields->f_cdisp10 = value;
+      break;
+    case MEP_OPERAND_CDISP10A2 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A2 :
-      fields->f_8s24a2 = value;
+    case MEP_OPERAND_CDISP10A4 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A4 :
-      fields->f_8s24a4 = value;
+    case MEP_OPERAND_CDISP10A8 :
+      fields->f_cdisp10 = value;
       break;
-    case MEP_OPERAND_CDISP8A8 :
-      fields->f_8s24a8 = value;
+    case MEP_OPERAND_CDISP12 :
+      fields->f_12s20 = value;
       break;
     case MEP_OPERAND_CIMM4 :
       fields->f_rn = value;
@@ -2198,6 +2314,9 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_RL :
       fields->f_rl = value;
       break;
+    case MEP_OPERAND_RL5 :
+      fields->f_rl5 = value;
+      break;
     case MEP_OPERAND_RM :
       fields->f_rm = value;
       break;
diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index aa25632b912..bd298cb38cb 100644
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -88,8 +88,8 @@ mep_config_map_struct mep_config_map[] =
 {
   /* config-map-start */
   /* Default entry: mep core only, all options enabled. */
-  { "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
-  { "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
+  { "", 0, EF_MEP_CPU_C5, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
+  { "default", CONFIG_DEFAULT, EF_MEP_CPU_C5, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
 	  0
 	| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
 	| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
@@ -120,6 +120,10 @@ check_configured_mach (int machs)
     case EF_MEP_CPU_H1:
       mach |= (1 << MACH_H1);
       break;
+    case EF_MEP_CPU_C5:
+      mach |= (1 << MACH_MEP);
+      mach |= (1 << MACH_C5);
+      break;
     default:
       break;
     }
@@ -172,6 +176,42 @@ static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
   0, 0, 0x0, { { 0 } }
 };
 
+static const CGEN_IFMT ifmt_stcb_r ATTRIBUTE_UNUSED = {
+  16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_pref ATTRIBUTE_UNUSED = {
+  16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_prefd ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_casb3 ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00ff0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_C5N4) }, { F (F_RL5) }, { F (F_C5N6) }, { F (F_C5N7) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sbcp ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00ff000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_12S20) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lbucpa ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lhucpa ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_uci ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dsp ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = {
   16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
 };
@@ -284,14 +324,6 @@ static const CGEN_IFMT ifmt_slt3i ATTRIBUTE_UNUSED = {
   16, 16, 0xf007, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_5U8) }, { F (F_SUB3) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_add3x ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_sltu3x ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_bra ATTRIBUTE_UNUSED = {
   16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_12S4A2) }, { F (F_15) }, { 0 } }
 };
@@ -348,14 +380,6 @@ static const CGEN_IFMT ifmt_bsetm ATTRIBUTE_UNUSED = {
   16, 16, 0xf80f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_3U5) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_tas ATTRIBUTE_UNUSED = {
-  16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cache ATTRIBUTE_UNUSED = {
-  16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_madd ATTRIBUTE_UNUSED = {
   32, 32, 0xf00fffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
 };
@@ -380,20 +404,12 @@ static const CGEN_IFMT ifmt_smcp16 ATTRIBUTE_UNUSED = {
   32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_sbcpa ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00fff00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_shcpa ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00fff01, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A2) }, { F (F_31) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_swcpa ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00fff03, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A4) }, { F (F_30) }, { F (F_31) }, { 0 } }
+  32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_smcpa ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00fff07, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A8) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } }
+  32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_bcpeq ATTRIBUTE_UNUSED = {
@@ -427,6 +443,132 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
   { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* stcb $rn,($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
+    & ifmt_stcb_r, { 0x700c }
+  },
+/* ldcb $rn,($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
+    & ifmt_stcb_r, { 0x700d }
+  },
+/* pref $cimm4,($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } },
+    & ifmt_pref, { 0x7005 }
+  },
+/* pref $cimm4,$sdisp16($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CIMM4), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } },
+    & ifmt_prefd, { 0xf0030000 }
+  },
+/* casb3 $rl5,$rn,($rm) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+    & ifmt_casb3, { 0xf0012000 }
+  },
+/* cash3 $rl5,$rn,($rm) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+    & ifmt_casb3, { 0xf0012001 }
+  },
+/* casw3 $rl5,$rn,($rm) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+    & ifmt_casb3, { 0xf0012002 }
+  },
+/* sbcp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf0060000 }
+  },
+/* lbcp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf0064000 }
+  },
+/* lbucp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf006c000 }
+  },
+/* shcp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf0061000 }
+  },
+/* lhcp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf0065000 }
+  },
+/* lhucp $crn,$cdisp12($rma) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+    & ifmt_sbcp, { 0xf006d000 }
+  },
+/* lbucpa $crn,($rma+),$cdisp10 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf005c000 }
+  },
+/* lhucpa $crn,($rma+),$cdisp10a2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf005d000 }
+  },
+/* lbucpm0 $crn,($rma+),$cdisp10 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf005c800 }
+  },
+/* lhucpm0 $crn,($rma+),$cdisp10a2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf005d800 }
+  },
+/* lbucpm1 $crn,($rma+),$cdisp10 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf005cc00 }
+  },
+/* lhucpm1 $crn,($rma+),$cdisp10a2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf005dc00 }
+  },
+/* uci $rn,$rm,$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
+    & ifmt_uci, { 0xf0020000 }
+  },
+/* dsp $rn,$rm,$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
+    & ifmt_dsp, { 0xf0000000 }
+  },
 /* sb $rnc,($rma) */
   {
     { 0, 0, 0, 0 },
@@ -743,19 +885,19 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } },
-    & ifmt_add3x, { 0xc0000000 }
+    & ifmt_uci, { 0xc0000000 }
   },
 /* slt3 $rn,$rm,$simm16 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } },
-    & ifmt_add3x, { 0xc0020000 }
+    & ifmt_uci, { 0xc0020000 }
   },
 /* sltu3 $rn,$rm,$uimm16 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
-    & ifmt_sltu3x, { 0xc0030000 }
+    & ifmt_dsp, { 0xc0030000 }
   },
 /* or $rn,$rm */
   {
@@ -785,19 +927,19 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
-    & ifmt_sltu3x, { 0xc0040000 }
+    & ifmt_dsp, { 0xc0040000 }
   },
 /* and3 $rn,$rm,$uimm16 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
-    & ifmt_sltu3x, { 0xc0050000 }
+    & ifmt_dsp, { 0xc0050000 }
   },
 /* xor3 $rn,$rm,$uimm16 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
-    & ifmt_sltu3x, { 0xc0060000 }
+    & ifmt_dsp, { 0xc0060000 }
   },
 /* sra $rn,$rm */
   {
@@ -1085,13 +1227,13 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
-    & ifmt_tas, { 0x2004 }
+    & ifmt_stcb_r, { 0x2004 }
   },
 /* cache $cimm4,($rma) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } },
-    & ifmt_cache, { 0x7004 }
+    & ifmt_pref, { 0x7004 }
   },
 /* mul $rn,$rm */
   {
@@ -1315,148 +1457,148 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } },
     & ifmt_smcp16, { 0xf00f0000 }
   },
-/* sbcpa $crn,($rma+),$cdisp8 */
+/* sbcpa $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0050000 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0050000 }
   },
-/* lbcpa $crn,($rma+),$cdisp8 */
+/* lbcpa $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0054000 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0054000 }
   },
-/* shcpa $crn,($rma+),$cdisp8a2 */
+/* shcpa $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0051000 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0051000 }
   },
-/* lhcpa $crn,($rma+),$cdisp8a2 */
+/* lhcpa $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0055000 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0055000 }
   },
-/* swcpa $crn,($rma+),$cdisp8a4 */
+/* swcpa $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0052000 }
   },
-/* lwcpa $crn,($rma+),$cdisp8a4 */
+/* lwcpa $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0056000 }
   },
-/* smcpa $crn64,($rma+),$cdisp8a8 */
+/* smcpa $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0053000 }
   },
-/* lmcpa $crn64,($rma+),$cdisp8a8 */
+/* lmcpa $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0057000 }
   },
-/* sbcpm0 $crn,($rma+),$cdisp8 */
+/* sbcpm0 $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0050800 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0050800 }
   },
-/* lbcpm0 $crn,($rma+),$cdisp8 */
+/* lbcpm0 $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0054800 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0054800 }
   },
-/* shcpm0 $crn,($rma+),$cdisp8a2 */
+/* shcpm0 $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0051800 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0051800 }
   },
-/* lhcpm0 $crn,($rma+),$cdisp8a2 */
+/* lhcpm0 $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0055800 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0055800 }
   },
-/* swcpm0 $crn,($rma+),$cdisp8a4 */
+/* swcpm0 $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0052800 }
   },
-/* lwcpm0 $crn,($rma+),$cdisp8a4 */
+/* lwcpm0 $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0056800 }
   },
-/* smcpm0 $crn64,($rma+),$cdisp8a8 */
+/* smcpm0 $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0053800 }
   },
-/* lmcpm0 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm0 $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0057800 }
   },
-/* sbcpm1 $crn,($rma+),$cdisp8 */
+/* sbcpm1 $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0050c00 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0050c00 }
   },
-/* lbcpm1 $crn,($rma+),$cdisp8 */
+/* lbcpm1 $crn,($rma+),$cdisp10 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
-    & ifmt_sbcpa, { 0xf0054c00 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+    & ifmt_lbucpa, { 0xf0054c00 }
   },
-/* shcpm1 $crn,($rma+),$cdisp8a2 */
+/* shcpm1 $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0051c00 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0051c00 }
   },
-/* lhcpm1 $crn,($rma+),$cdisp8a2 */
+/* lhcpm1 $crn,($rma+),$cdisp10a2 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
-    & ifmt_shcpa, { 0xf0055c00 }
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+    & ifmt_lhucpa, { 0xf0055c00 }
   },
-/* swcpm1 $crn,($rma+),$cdisp8a4 */
+/* swcpm1 $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0052c00 }
   },
-/* lwcpm1 $crn,($rma+),$cdisp8a4 */
+/* lwcpm1 $crn,($rma+),$cdisp10a4 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+    { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
     & ifmt_swcpa, { 0xf0056c00 }
   },
-/* smcpm1 $crn64,($rma+),$cdisp8a8 */
+/* smcpm1 $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0053c00 }
   },
-/* lmcpm1 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm1 $crn64,($rma+),$cdisp10a8 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+    { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
     & ifmt_smcpa, { 0xf0057c00 }
   },
 /* bcpeq $cccc,$pcrel17a2 */
@@ -1633,42 +1775,12 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, 0 } },
     & ifmt_mov, { 0xe00d }
   },
-/* --reserved-- */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_mov, { 0xf003 }
-  },
-/* --reserved-- */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_mov, { 0xf006 }
-  },
 /* --reserved-- */
   {
     { 0, 0, 0, 0 },
     { { MNEM, 0 } },
     & ifmt_mov, { 0xf008 }
   },
-/* --reserved-- */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_mov, { 0x7005 }
-  },
-/* --reserved-- */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_mov, { 0x700c }
-  },
-/* --reserved-- */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_mov, { 0x700d }
-  },
 };
 
 #undef A
@@ -1683,6 +1795,14 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
 #else
 #define F(f) & mep_cgen_ifld_table[MEP_/**/f]
 #endif
+static const CGEN_IFMT ifmt_dsp0 ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dsp1 ATTRIBUTE_UNUSED = {
+  32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
   16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
 };
@@ -1756,6 +1876,16 @@ static const CGEN_IFMT ifmt_lmcp16_0 ATTRIBUTE_UNUSED = {
 
 static const CGEN_IBASE mep_cgen_macro_insn_table[] =
 {
+/* dsp0 $c5rnmuimm24 */
+  {
+    -1, "dsp0", "dsp0", 32,
+    { 0|A(VOLATILE)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
+/* dsp1 $rn,$c5rmuimm20 */
+  {
+    -1, "dsp1", "dsp1", 32,
+    { 0|A(VOLATILE)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+  },
 /* nop */
   {
     -1, "nop", "nop", 16,
@@ -1827,6 +1957,18 @@ static const CGEN_IBASE mep_cgen_macro_insn_table[] =
 
 static const CGEN_OPCODE mep_cgen_macro_insn_opcode_table[] =
 {
+/* dsp0 $c5rnmuimm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (C5RNMUIMM24), 0 } },
+    & ifmt_dsp0, { 0xf0000000 }
+  },
+/* dsp1 $rn,$c5rmuimm20 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), ',', OP (C5RMUIMM20), 0 } },
+    & ifmt_dsp1, { 0xf0000000 }
+  },
 /* nop */
   {
     { 0, 0, 0, 0 },
diff --git a/opcodes/mep-opc.h b/opcodes/mep-opc.h
index 20a81696a05..5e56923eba5 100644
--- a/opcodes/mep-opc.h
+++ b/opcodes/mep-opc.h
@@ -96,65 +96,69 @@ extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 /* -- asm.c */
 /* Enum declaration for mep instruction types.  */
 typedef enum cgen_insn_type {
-  MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW
- , MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU
- , MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP
- , MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP
- , MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16
- , MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16
- , MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24
- , MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB
- , MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8
- , MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH
- , MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3
- , MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3
- , MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3
- , MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X
- , MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR
- , MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA
- , MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI
- , MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA
- , MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI
- , MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE
- , MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24
- , MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT
- , MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC
- , MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC
- , MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT
- , MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM
- , MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM
- , MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE
- , MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU
- , MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU
- , MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK
- , MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN
- , MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP
- , MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU
- , MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP
- , MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI
- , MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16
- , MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA
- , MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA
- , MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0
- , MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0
- , MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1
- , MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1
- , MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT
- , MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV
- , MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2
- , MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6
- , MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10
- , MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14
- , MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21
- , MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25
- , MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19
+  MEP_INSN_INVALID, MEP_INSN_STCB_R, MEP_INSN_LDCB_R, MEP_INSN_PREF
+ , MEP_INSN_PREFD, MEP_INSN_CASB3, MEP_INSN_CASH3, MEP_INSN_CASW3
+ , MEP_INSN_SBCP, MEP_INSN_LBCP, MEP_INSN_LBUCP, MEP_INSN_SHCP
+ , MEP_INSN_LHCP, MEP_INSN_LHUCP, MEP_INSN_LBUCPA, MEP_INSN_LHUCPA
+ , MEP_INSN_LBUCPM0, MEP_INSN_LHUCPM0, MEP_INSN_LBUCPM1, MEP_INSN_LHUCPM1
+ , MEP_INSN_UCI, MEP_INSN_DSP, MEP_INSN_SB, MEP_INSN_SH
+ , MEP_INSN_SW, MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW
+ , MEP_INSN_LBU, MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP
+ , MEP_INSN_SB_TP, MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP
+ , MEP_INSN_LH_TP, MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP
+ , MEP_INSN_SB16, MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16
+ , MEP_INSN_LH16, MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16
+ , MEP_INSN_SW24, MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH
+ , MEP_INSN_EXTUB, MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV
+ , MEP_INSN_MOVI8, MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16
+ , MEP_INSN_MOVH, MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I
+ , MEP_INSN_ADVCK3, MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG
+ , MEP_INSN_SLT3, MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I
+ , MEP_INSN_SL1AD3, MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X
+ , MEP_INSN_SLTU3X, MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR
+ , MEP_INSN_NOR, MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3
+ , MEP_INSN_SRA, MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI
+ , MEP_INSN_SRLI, MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT
+ , MEP_INSN_BRA, MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI
+ , MEP_INSN_BNEI, MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ
+ , MEP_INSN_BNE, MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP
+ , MEP_INSN_JMP24, MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT
+ , MEP_INSN_EREPEAT, MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO
+ , MEP_INSN_STC, MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO
+ , MEP_INSN_LDC, MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI
+ , MEP_INSN_HALT, MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK
+ , MEP_INSN_SYNCM, MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM
+ , MEP_INSN_BCLRM, MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS
+ , MEP_INSN_CACHE, MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR
+ , MEP_INSN_MULRU, MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR
+ , MEP_INSN_MADDRU, MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET
+ , MEP_INSN_DBREAK, MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE
+ , MEP_INSN_MIN, MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU
+ , MEP_INSN_CLIP, MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB
+ , MEP_INSN_SADDU, MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP
+ , MEP_INSN_SMCP, MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI
+ , MEP_INSN_SMCPI, MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16
+ , MEP_INSN_SMCP16, MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA
+ , MEP_INSN_SHCPA, MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA
+ , MEP_INSN_SMCPA, MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0
+ , MEP_INSN_SHCPM0, MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0
+ , MEP_INSN_SMCPM0, MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1
+ , MEP_INSN_SHCPM1, MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1
+ , MEP_INSN_SMCPM1, MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE
+ , MEP_INSN_BCPAT, MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV
+ , MEP_INSN_BSRV, MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1
+ , MEP_INSN_RI_2, MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5
+ , MEP_INSN_RI_6, MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9
+ , MEP_INSN_RI_10, MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13
+ , MEP_INSN_RI_14, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20
+ , MEP_INSN_RI_21, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_26
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
 #define CGEN_INSN_INVALID MEP_INSN_INVALID
 
 /* Total number of insns in table.  */
-#define MAX_INSNS ((int) MEP_INSN_RI_19 + 1)
+#define MAX_INSNS ((int) MEP_INSN_RI_26 + 1)
 
 /* This struct records data prior to insertion or after extraction.  */
 struct cgen_fields
@@ -171,6 +175,8 @@ struct cgen_fields
   long f_sub3;
   long f_sub4;
   long f_ext;
+  long f_ext4;
+  long f_ext62;
   long f_crn;
   long f_csrn_hi;
   long f_csrn_lo;
@@ -234,10 +240,7 @@ struct cgen_fields
   long f_16u16;
   long f_12u16;
   long f_3u29;
-  long f_8s24;
-  long f_8s24a2;
-  long f_8s24a4;
-  long f_8s24a8;
+  long f_cdisp10;
   long f_24u8a4n_hi;
   long f_24u8a4n_lo;
   long f_24u8a4n;
@@ -251,6 +254,17 @@ struct cgen_fields
   long f_ccrn_hi;
   long f_ccrn_lo;
   long f_ccrn;
+  long f_c5n4;
+  long f_c5n5;
+  long f_c5n6;
+  long f_c5n7;
+  long f_rl5;
+  long f_12s20;
+  long f_c5_rnm;
+  long f_c5_rm;
+  long f_c5_16u16;
+  long f_c5_rmuimm20;
+  long f_c5_rnmuimm24;
 };
 
 #define CGEN_INIT_PARSE(od) \