From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Nov 2013 23:58:06 +0000 (+0100)
Subject: Fixed techmap of $reduce_xnor with multi-bit outputs
X-Git-Tag: yosys-0.2.0~396
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=404b46674b3bfec73ecac484bbf56354fd66f2c8;p=yosys.git

Fixed techmap of $reduce_xnor with multi-bit outputs
---

diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index ca73f5bcd..e37ad20d5 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -351,9 +351,15 @@ endgenerate
 assign buffer[0] = A[0];
  \$_INV_ gate_inv (
 	.A(buffer[A_WIDTH-1]),
-	.Y(Y)
+	.Y(Y[0])
 );
 
+generate
+	if (Y_WIDTH > 1) begin:V
+		assign Y[Y_WIDTH-1:1] = 0;
+	end
+endgenerate
+
 endmodule
 
 // --------------------------------------------------------