From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 15 Feb 2016 08:40:04 +0000 (-0500)
Subject: mem: Avoid using invalid iterator in cache lock list traversal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=407233f5d80d04e27234eb70750a7f6ee13acd4f;p=gem5.git

mem: Avoid using invalid iterator in cache lock list traversal

Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
---

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 6682dd4bb..39d45d6e1 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -347,15 +347,16 @@ class CacheBlk
             bool success = false;
 
             auto l = lockList.begin();
-            while (l != lockList.end() && !success) {
+            while (!success && l != lockList.end()) {
                 if (l->matches(pkt->req)) {
                     // it's a store conditional, and as far as the
                     // memory system can tell, the requesting
                     // context's lock is still valid.
                     success = true;
                     lockList.erase(l);
+                } else {
+                    ++l;
                 }
-                ++l;
             }
 
             req->setExtraData(success ? 1 : 0);