From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 May 2023 13:31:13 +0000 (+0100)
Subject: add FPSCR to Test API (ExpectedState, SimState). untested
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4072f840ada2e6ee1a9ec38ab8c7d9f608ed807d;p=openpower-isa.git

add FPSCR to Test API (ExpectedState, SimState). untested
---

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index 07827e76..aa61d94b 100644
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -73,6 +73,7 @@ class State:
     memory - stored as a dictionary {location: data}
     """
     def get_state(self):
+        yield from self.get_fpscr()
         yield from self.get_fpregs()
         yield from self.get_intregs()
         yield from self.get_crregs()
@@ -130,6 +131,11 @@ class State:
         self.dut.assertEqual(self.pc, s2.pc, "pc mismatch (%s != %s) %s" %
             (self.state_type, s2.state_type, repr(self.code)))
 
+        # fpscr
+        self.dut.assertEqual(self.fpscr, s2.fpscr,
+                             "fpscr mismatch (%s != %s) %s" %
+            (self.state_type, s2.state_type, repr(self.code)))
+
     def compare_mem(self, s2):
         # copy dics to preserve state mem then pad empty locs since
         # different Power ISA objects may differ how theystore memory
@@ -210,6 +216,12 @@ class SimState(State):
         self.fpregs = _get_regs(self.sim.fpr)
         log("class sim fp regs", list(map(hex, self.fpregs)))
 
+    def get_fpscr(self):
+        if False:
+            yield
+        self.fpscr = self.sim.fpscr.value
+        log("class sim fpscr", hex(self.fpscr))
+
     def get_intregs(self):
         if False:
             yield
@@ -267,12 +279,13 @@ class ExpectedState(State):
     see openpower/test/shift_rot/shift_rot_cases2.py for examples
     """
     def __init__(self, int_regs=None, pc=0, crregs=None,
-                 so=0, ov=0, ca=0, fp_regs=None):
+                 so=0, ov=0, ca=0, fp_regs=None, fpscr=0):
         if fp_regs is None:
             fp_regs = 32
         if isinstance(fp_regs, int):
             fp_regs = [0] * fp_regs
         self.fpregs = deepcopy(fp_regs)
+        self.fpscr = fpscr
         if int_regs is None:
             int_regs = 32
         if isinstance(int_regs, int):
@@ -290,6 +303,8 @@ class ExpectedState(State):
 
     def get_fpregs(self):
         if False: yield
+    def get_fpscr(self):
+        if False: yield
     def get_intregs(self):
         if False: yield
     def get_crregs(self):