From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Jul 2015 12:13:41 +0000 (+0200)
Subject: litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
X-Git-Tag: 24jan2021_ls180~2202
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40740d3ddc044d9eb7a075d33cab404e34ae9c40;p=litex.git

litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files

We should eventually try to use python package_data or data_file for that.
---

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index 90f3ec88..b88e8092 100644
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -69,6 +69,7 @@ class PCIeDMASoC(SoC, AutoCSR):
             with_timer=False
         )
         self.submodules.crg = _CRG(platform)
+        platform.misoc_path = "../../../../"
 
         # PCIe endpoint
         self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
diff --git a/misoclib/com/litepcie/phy/s7pciephy.py b/misoclib/com/litepcie/phy/s7pciephy.py
index 80c7763c..40869213 100644
--- a/misoclib/com/litepcie/phy/s7pciephy.py
+++ b/misoclib/com/litepcie/phy/s7pciephy.py
@@ -151,15 +151,13 @@ class S7PCIEPHY(Module, AutoCSR):
             convert_size(dcommand[12:15], self.max_request_size),
             convert_size(dcommand[5:8], self.max_payload_size)
         ]
-
-        extcores_path = "extcores"
-        # XXX find a better way to do this?
-        current_path = os.getcwd()
-        current_path = current_path.replace("\\", "/")
-        if "litepcie/example_designs" in current_path:
-            extcores_path = os.path.join("..", "..", "..", "..", extcores_path)
-        platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "common"))
+        if hasattr(platform, "misoc_path"):
+            misoc_path = platform.misoc_path
+        else:
+            misoc_path = "./"
+        litepcie_phy_wrapper_path = os.path.join(misoc_path, "extcores", "litepcie_phy_wrappers")
+        platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "common"))
         if device[:4] == "xc7k":
-            platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "kintex7"))
+            platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "kintex7"))
         elif device[:4] == "xc7a":
-            platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "artix7"))
+            platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "artix7"))