From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 27 Jul 2009 07:53:10 +0000 (-0700)
Subject: ARM: Add in spots for the VFP control registers.
X-Git-Tag: Calvin_Submission~194^2~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4079792f2b61bd1e7c46a5aa8ddb06974982d1db;p=gem5.git

ARM: Add in spots for the VFP control registers.
---

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 6e6eea5a8..ac7427dad 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -82,7 +82,10 @@ def operands {{
 
     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
-    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
-    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
+    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
+    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
+    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
+    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
+    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
 
 }};
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 42065b0fd..3180669de 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -62,6 +62,9 @@ namespace ArmISA
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
         MISCREG_FPSR,
+        MISCREG_FPSID,
+        MISCREG_FPSCR,
+        MISCREG_FPEXC,
 	NUM_MISCREGS
     };