From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 11:56:24 +0000 (+0200)
Subject: litescope: more pep8 (when convenient), should be almost OK
X-Git-Tag: 24jan2021_ls180~2350
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40abd66d6921668dddac21a9fbc925a62600ee01;p=litex.git

litescope: more pep8 (when convenient), should be almost OK
---

diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py
index 64cd1186..08e4ec03 100644
--- a/misoclib/tools/litescope/bridge/uart2wb.py
+++ b/misoclib/tools/litescope/bridge/uart2wb.py
@@ -23,7 +23,7 @@ class UARTMux(Module):
         self.bridge_pads = UARTPads()
 
         # # #
-	
+
         # Route rx pad:
         # when sel==0, route it to shared rx and bridge rx
         # when sel==1, route it only to bridge rx
@@ -51,13 +51,14 @@ class LiteScopeUART2WB(Module, AutoCSR):
         "write": 0x01,
         "read": 0x02
     }
+
     def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
         self.wishbone = wishbone.Interface()
         if share_uart:
             self._sel = CSRStorage()
-        
-		# # #
-		
+
+        # # #
+
         if share_uart:
             mux = UARTMux(pads)
             uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate)
diff --git a/misoclib/tools/litescope/core/storage.py b/misoclib/tools/litescope/core/storage.py
index 76c6735b..7990ad17 100644
--- a/misoclib/tools/litescope/core/storage.py
+++ b/misoclib/tools/litescope/core/storage.py
@@ -136,19 +136,25 @@ class LiteScopeRecorderUnit(Module):
             data_sink.ack.eq(fifo.sink.ack),
 
             fifo.source.ack.eq(fifo.fifo.level >= self.offset),
-            If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
+            If(trigger_sink.stb & trigger_sink.hit,
+                NextState("POST_HIT_RECORDING")
+            )
         )
         fsm.act("POST_HIT_RECORDING",
             self.post_hit.eq(1),
             If(self.qualifier,
-                fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
+                fifo.sink.stb.eq(trigger_sink.stb &
+                                 trigger_sink.hit &
+                                 data_sink.stb)
             ).Else(
                 fifo.sink.stb.eq(data_sink.stb)
             ),
             fifo.sink.data.eq(data_sink.data),
             data_sink.ack.eq(fifo.sink.ack),
 
-            If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
+            If(~fifo.sink.ack | (fifo.fifo.level >= self.length),
+                NextState("IDLE")
+            )
         )
 
 
diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index bd7897cf..dfc0f348 100644
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -15,6 +15,7 @@ class LiteScopeSoC(SoC, AutoCSR):
         "la":    17
     }
     csr_map.update(SoC.csr_map)
+
     def __init__(self, platform):
         clk_freq = int((1/(platform.default_clk_period))*1000000000)
         SoC.__init__(self, platform, clk_freq,
diff --git a/misoclib/tools/litescope/example_designs/test/test_io.py b/misoclib/tools/litescope/example_designs/test/test_io.py
index fb853b02..ddfd30c5 100644
--- a/misoclib/tools/litescope/example_designs/test/test_io.py
+++ b/misoclib/tools/litescope/example_designs/test/test_io.py
@@ -17,13 +17,13 @@ def led_anim1(io):
         for i in range(8):
             io.write(led_data)
             time.sleep(i*i*0.0020)
-            led_data = (led_data<<1)
+            led_data = (led_data << 1)
         # Led >>
         ledData = 128
         for i in range(8):
             io.write(led_data)
             time.sleep(i*i*0.0020)
-            led_data = (led_data>>1)
+            led_data = (led_data >> 1)
 
 
 def main(wb):
diff --git a/misoclib/tools/litescope/frontend/la.py b/misoclib/tools/litescope/frontend/la.py
index a216c35b..4ba2c039 100644
--- a/misoclib/tools/litescope/frontend/la.py
+++ b/misoclib/tools/litescope/frontend/la.py
@@ -48,7 +48,8 @@ class LiteScopeLA(Module, AutoCSR):
         # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
         if self.clk_domain is not "sys":
             self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
-            self.submodules += RenameClockDomains(self.fifo, {"write": self.clk_domain, "read": "sys"})
+            self.submodules += RenameClockDomains(self.fifo,
+                {"write": self.clk_domain, "read": "sys"})
             self.comb += Record.connect(sink, self.fifo.sink)
             sink = self.fifo.source
 
diff --git a/misoclib/tools/litescope/host/dump/vcd.py b/misoclib/tools/litescope/host/dump/vcd.py
index d3fd6d3e..a27294cf 100644
--- a/misoclib/tools/litescope/host/dump/vcd.py
+++ b/misoclib/tools/litescope/host/dump/vcd.py
@@ -33,25 +33,25 @@ class VCDDump(Dump):
         return r
 
     def generate_version(self):
-        r  = "$version\n"
+        r = "$version\n"
         r += "\tmiscope VCD dump\n"
         r += "$end\n"
         return r
 
     def generate_comment(self):
-        r  = "$comment\n"
+        r = "$comment\n"
         r += self.comment
         r += "\n$end\n"
         return r
 
     def generate_timescale(self):
-        r  = "$timescale "
+        r = "$timescale "
         r += self.timescale
         r += " $end\n"
         return r
 
     def generate_scope(self):
-        r  = "$scope "
+        r = "$scope "
         r += self.timescale
         r += " $end\n"
         return r
@@ -71,17 +71,17 @@ class VCDDump(Dump):
         return r
 
     def generate_unscope(self):
-        r  = "$unscope "
+        r = "$unscope "
         r += " $end\n"
         return r
 
     def generate_enddefinitions(self):
-        r  = "$enddefinitions "
+        r = "$enddefinitions "
         r += " $end\n"
         return r
 
     def generate_dumpvars(self):
-        r  = "$dumpvars\n"
+        r = "$dumpvars\n"
         for var in self.vars:
             r += "b"
             r += dec2bin(var.val, var.width)