From: akshara <akshara@web>
Date: Mon, 23 Aug 2021 04:20:36 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40b0a30f1f58d4ee620641b9a1110aab20006746;p=libreriscv.git

---

diff --git a/about_us.mdwn b/about_us.mdwn
index d36713bf4..5db025edf 100644
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -168,12 +168,6 @@ TODO, Adithya
 * Programming Languages: C, Python, Java, VHDL
 * Availability: ~8-10 hours/week
 
-### [[oa/Akshara S]]
-
-* Interests: Embedded systems, Analog Electronics
-* Programming Languages: C, Python, Verilog
-* Availability: ~ 3-4 hours/week
-
 ### [[oa/Sukhanshu D]]
 
 * Experience: SOC Verification Intern, Digital Design
@@ -185,11 +179,7 @@ TODO, Adithya
 * Interests: Digital Design, Verification, IC Fabrication
 * Programming Languages: Verilog, System Verilog, UVM
 * Availability: ~ 6-8 hours/week
-* Experience: SoC Verification Intern, Research Intern at KIST
-
-### [[oa/sparsha]]
-
-TODO
+* Experience: SoC Verification Intern, Research Intern at KIS
 
 ## 3mdeb