From: Joanna Brozek <jbrozek@antmicro.com>
Date: Fri, 12 Apr 2019 15:23:23 +0000 (+0200)
Subject: vexriscv: Add full and full_debug CPU variant
X-Git-Tag: 24jan2021_ls180~1326^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40de01bcb0a9bf5992602e8fc50e338fc2c07dff;p=litex.git

vexriscv: Add full and full_debug CPU variant
---

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 5a1afedc..c4c0df65 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -16,7 +16,7 @@ class VexRiscv(Module, AutoCSR):
     def __init__(self, platform, cpu_reset_address, variant=None):
         variant = "std" if variant is None else variant
         variant = "std_debug" if variant == "debug" else variant
-        variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
+        variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug", "full", "full_debug")
         assert variant in variants, "Unsupported variant %s" % variant
         self.platform = platform
         self.variant = variant
@@ -157,6 +157,8 @@ class VexRiscv(Module, AutoCSR):
             "lite_debug": "VexRiscv_LiteDebug.v",
             "min":        "VexRiscv_Min.v",
             "min_debug":  "VexRiscv_MinDebug.v",
+            "full":       "VexRiscv_Full.v",
+            "full_debug": "VexRiscv_FullDebug.v",
         }
         cpu_filename = verilog_variants[variant]
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index d7bbc2c1..ebe40646 160000
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be
+Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5