From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Mon, 25 May 2020 00:14:04 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40ee401c05ddf0b1cfad7cccfc4cff932b206b12;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
---

diff --git a/8f/d3f60617ab7e2a5e1afccd25fa6c1a914e74a9 b/8f/d3f60617ab7e2a5e1afccd25fa6c1a914e74a9
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@@ -0,0 +1,69 @@
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+Date: Mon, 25 May 2020 00:14:04 +0000
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+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-350-13-tz5gvKmpfX@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support
+ zeroing on RA
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