From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Feb 2015 11:58:12 +0000 (+0100)
Subject: Added "check -noinit"
X-Git-Tag: yosys-0.6~430
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40f021e1367af8cc8cd2ea133ba4cb0d2f342cbd;p=yosys.git

Added "check -noinit"
---

diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 6840572eb..824131a7a 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -31,7 +31,7 @@ struct CheckPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    check [selection]\n");
+		log("    check [options] [selection]\n");
 		log("\n");
 		log("This pass identifies the following problems in the current design:\n");
 		log("\n");
@@ -41,14 +41,26 @@ struct CheckPass : public Pass {
 		log("\n");
 		log(" - used wires that do not have a driver\n");
 		log("\n");
+		log("When called with -noinit then this command also checks for wires which have\n");
+		log("the 'init' attribute set.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		int counter = 0;
+		bool noinit = false;
 
-		log_header("Executing CHECK pass (checking for obvious problems).\n");
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-noinit") {
+				noinit = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
 
-		extra_args(args, 1, design);
+		log_header("Executing CHECK pass (checking for obvious problems).\n");
 
 		for (auto module : design->selected_whole_modules_warn())
 		{
@@ -93,6 +105,10 @@ struct CheckPass : public Pass {
 				if (wire->port_output)
 					for (auto bit : sigmap(wire))
 						if (bit.wire) used_wires.insert(bit);
+				if (noinit && wire->attributes.count("\\init")) {
+					log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
+					counter++;
+				}
 			}
 
 			for (auto it : wire_drivers)