From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Apr 2020 12:41:01 +0000 (+0200)
Subject: targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
X-Git-Tag: 24jan2021_ls180~467
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=40f43efcf661e87fa278ebcfe22a7c869ad02fd7;p=litex.git

targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
---

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 91206fa2..5830f35e 100755
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -8,6 +8,8 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
+
 from litex.boards.platforms import de0nano
 
 from litex.soc.cores.clock import CycloneIVPLL
@@ -38,7 +40,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
 
         # SDRAM clock
-        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 408ed442..638d28d1 100755
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -12,6 +12,7 @@ from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import DDROutput
+
 from litex.boards.platforms import minispartan6
 
 from litex.soc.cores.clock import *
@@ -37,7 +38,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
 
         # SDRAM clock
-        self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps"))
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
@@ -53,7 +54,7 @@ class BaseSoC(SoCCore):
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
                 module                  = AS4C16M16(sys_clk_freq, "1:1"),
diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 98a5f30a..e42c92b0 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -10,6 +10,8 @@ import sys
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
+
 from litex.boards.platforms import ulx3s
 
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
@@ -45,7 +47,7 @@ class _CRG(Module):
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
 
         # SDRAM clock
-        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
         # Prevent ESP32 from resetting FPGA
         self.comb += platform.request("wifi_gpio0").eq(1)