From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 23:32:35 +0000 (+0100)
Subject: use PipeModBase in float2int fcvt
X-Git-Tag: ls180-24jan2020~582
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=410c24fde640a0214db78e8a5ac38a7896b7a8be;p=ieee754fpu.git

use PipeModBase in float2int fcvt
---

diff --git a/src/ieee754/fcvt/float2int.py b/src/ieee754/fcvt/float2int.py
index d28ab19d..dc2f19b8 100644
--- a/src/ieee754/fcvt/float2int.py
+++ b/src/ieee754/fcvt/float2int.py
@@ -1,18 +1,20 @@
 # IEEE754 Floating Point Converter
 # Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
+from nmigen import Module, Signal, Cat, Const, Mux
 from nmigen.cli import main, verilog
 
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import Overflow
 from ieee754.fpcommon.basedata import FPBaseData
+from ieee754.fpcommon.packdata import FPPackData
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.exphigh import FPEXPHigh
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTFloatToIntMod(Elaboratable):
+class FPCVTFloatToIntMod(PipeModBase):
     """ integer to FP conversion: copes with 16/32/64 fp to 16/32/64 int/uint
 
         self.ctx.i.op & 0x1 == 0x1 : SIGNED int
@@ -23,8 +25,7 @@ class FPCVTFloatToIntMod(Elaboratable):
     def __init__(self, in_pspec, out_pspec):
         self.in_pspec = in_pspec
         self.out_pspec = out_pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(in_pspec, "fp2int")
 
     def ispec(self):
         return FPBaseData(self.in_pspec)
@@ -32,15 +33,6 @@ class FPCVTFloatToIntMod(Elaboratable):
     def ospec(self):
         return FPPackData(self.out_pspec)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.upconvert = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
diff --git a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
index bac4824d..727c1ae3 100644
--- a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
+++ b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
@@ -148,7 +148,6 @@ if __name__ == '__main__':
         test_int_pipe_f16_i16()
         test_int_pipe_f32_i32()
         test_int_pipe_f64_i64()
-        continue
         test_int_pipe_f64_ui64()
         test_int_pipe_f32_ui32()
         test_int_pipe_f16_ui16()