From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 29 Jul 2016 21:47:26 +0000 (-0700)
Subject: Add RV32 RVC and breakpoint tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4117bf6b12b2de928ca19e9638376f75f7be6d7e;p=riscv-tests.git

Add RV32 RVC and breakpoint tests
---

diff --git a/isa/Makefile b/isa/Makefile
index b836bbd..f4dab3f 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -15,6 +15,7 @@ include $(src_dir)/rv64ud/Makefrag
 include $(src_dir)/rv64si/Makefrag
 include $(src_dir)/rv64mi/Makefrag
 include $(src_dir)/rv32ui/Makefrag
+include $(src_dir)/rv32uc/Makefrag
 include $(src_dir)/rv32um/Makefrag
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32si/Makefrag
@@ -68,6 +69,7 @@ tests += $$($(1)_tests)
 endef
 
 $(eval $(call compile_template,rv32ui,-m32))
+$(eval $(call compile_template,rv32uc,-m32))
 $(eval $(call compile_template,rv32um,-m32))
 $(eval $(call compile_template,rv32ua,-m32))
 $(eval $(call compile_template,rv32si,-m32))
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 636e097..a726244 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -3,11 +3,12 @@
 #-----------------------------------------------------------------------
 
 rv32mi_sc_tests = \
+	breakpoint \
 	csr \
+	mcsr \
 	illegal \
 	ma_fetch \
 	ma_addr \
-	mcsr \
 	scall \
 	sbreak \
 	shamt \
diff --git a/isa/rv32mi/breakpoint.S b/isa/rv32mi/breakpoint.S
new file mode 100644
index 0000000..ecbec6a
--- /dev/null
+++ b/isa/rv32mi/breakpoint.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64mi/breakpoint.S"
diff --git a/isa/rv32uc/Makefrag b/isa/rv32uc/Makefrag
new file mode 100644
index 0000000..0586843
--- /dev/null
+++ b/isa/rv32uc/Makefrag
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv32uc tests
+#-----------------------------------------------------------------------
+
+rv32uc_sc_tests = \
+	rvc \
+
+rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
+rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
+
+spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
diff --git a/isa/rv32uc/rvc.S b/isa/rv32uc/rvc.S
new file mode 100644
index 0000000..debbbd8
--- /dev/null
+++ b/isa/rv32uc/rvc.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uc/rvc.S"
diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S
index 4f2675a..6e3cf33 100644
--- a/isa/rv64uc/rvc.S
+++ b/isa/rv64uc/rvc.S
@@ -47,8 +47,11 @@ RVTEST_CODE_BEGIN
 #endif
 
   RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12)
+#ifdef __riscv64
   RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
-  RVC_TEST_CASE (13, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#else
+  RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#endif
   RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10)
   RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0)
   RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0)