From: lkcl <lkcl@web>
Date: Fri, 6 Aug 2021 19:59:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~469
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=411f318aec265ae8ff56e95990e0511acbb46abb;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index bafb0b57b..e281a3149 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -119,9 +119,10 @@ Fields:
   included. SVSTATE.MVL is not changed: only VL.
 * **LRu**: Link Register Update. When set, Link Register will
   only be updated if the Branch Condition succeeds. This avoids
-  destruction of LR during loops.
+  destruction of LR during loops (particularly Vertical-First
+  ones).
 * **BRc** Branch variant of Rc. Instructs svstep testing to overwrite
-  the CR Field about to be tested
+  the CR Field about to be tested. Only takes effect in svstep mode
 * **VSb** is most relevant for Vertical-First VLSET Mode. After testing,
   if VSb is set, VL is truncated if the branch succeeds.  If VSb is clear,
   VL is truncated if the branch did **not** take place.